Complete 8-Bit, 32 MSPS, 95 mW a CMOS A/D Converter AD9280 FEATURES A single clock input is used to control all internal conversion CMOS 8-Bit 32 MSPS Sampling A/D Converter cycles. The digital output data is presented in straight binary Pin-Compatible with AD876-8 output format. An out-of-range signal (OTR) indicates an over- Power Dissipation: 95 mW (3 V Supply) flow condition which can be used with the most significant bit Operation Between +2.7 V and +5.5 V Supply to determine low or high overflow. Differential Nonlinearity: 0.2 LSB The AD9280 can operate with a supply range from +2.7 V to Power-Down (Sleep) Mode +5.5 V, ideally suiting it for low power operation in high speed Three-State Outputs applications. Out-of-Range Indicator The AD9280 is specified over the industrial (40C to +85C) Built-In Clamp Function (DC Restore) temperature range. Adjustable On-Chip Voltage Reference IF Undersampling to 135 MHz PRODUCT HIGHLIGHTS PRODUCT DESCRIPTION Low Power The AD9280 is a monolithic, single supply, 8-bit, 32 MSPS The AD9280 consumes 95 mW on a 3 V supply (excluding the analog-to-digital converter with an on-chip sample-and-hold reference power). In sleep mode, power is reduced to below amplifier and voltage reference. The AD9280 uses a multistage 5 mW. differential pipeline architecture at 32 MSPS data rates and Very Small Package guarantees no missing codes over the full operating temperature The AD9280 is available in a 28-lead SSOP package. range. Pin Compatible with AD876-8 The input of the AD9280 has been designed to ease the devel- The AD9280 is pin compatible with the AD876-8, allowing opment of both imaging and communications systems. The user older designs to migrate to lower supply voltages. can select a variety of input ranges and offsets and can drive the 300 MHz Onboard Sample-and-Hold input either single-ended or differentially. The versatile SHA input can be configured for either single- The sample-and-hold amplifier (SHA) is equally suited for both ended or differential inputs. multiplexed systems that switch full-scale voltage levels in suc- Out-of-Range Indicator cessive channels and sampling single-channel inputs at frequen- The OTR output bit indicates when the input signal is beyond cies up to and beyond the Nyquist rate. AC-coupled input the AD9280s input range. signals can be shifted to a predetermined level, with an onboard clamp circuit. The dynamic performance is excellent. Built-In Clamp Function Allows dc restoration of video signals. The AD9280 has an onboard programmable reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. FUNCTIONAL BLOCK DIAGRAM CLAMP CLAMP CLK AVDD DRVDD IN STBY SHA SHA GAIN SHA GAIN SHA GAIN SHA GAIN MODE VINA A/D REFTF THREE- A/D D/A A/D D/A A/D D/A A/D D/A REFTS STATE CORRECTION LOGIC REFBS REFBF OUTPUT BUFFERS OTR VREF D7 (MSB) AD9280 1V REFSENSE D0 (LSB) AVSS DRVSS REV. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: (AVDD = +3 V, DRVDD = +3 V, F = 32 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input S AD9280SPECIFICATIONS Span from 0.5 V to 2.5 V, External Reference, T to T unless otherwise noted) MIN MAX Parameter Symbol Min Typ Max Units Condition RESOLUTION 8 Bits CONVERSION RATE F 32 MHz S DC ACCURACY Differential Nonlinearity DNL 0.2 1.0 LSB REFTS = 2.5 V, REFBS = 0.5 V Integral Nonlinearity INL 0.3 1.5 LSB Offset Error E 0.2 1.8 % FSR ZS Gain Error E 1.2 3.9 % FSR FS REFERENCE VOLTAGES Top Reference Voltage REFTS 1 AVDD V Bottom Reference Voltage REFBS GND AVDD 1 V Differential Reference Voltage 2 V p-p 1 Reference Input Resistance 10 k REFTS, REFBS: MODE = AVDD 4.2 k Between REFTF & REFBF: MODE = AVSS ANALOG INPUT Input Voltage Range AIN REFBS REFTS V REFBS Min = GND: REFTS Max = AVDD Input Capacitance C 1 pF Switched IN Aperture Delay t 4ns AP Aperture Uncertainty (Jitter) t 2ps AJ Input Bandwidth (3 dB) BW Full Power (0 dB) 300 MHz DC Leakage Current 43 A Input = FS INTERNAL REFERENCE Output Voltage (1 V Mode) VREF 1 V REFSENSE = VREF Output Voltage Tolerance (1 V Mode) 10 25 mV Output Voltage (2 V Mode) VREF 2 V REFSENSE = GND Load Regulation (1 V Mode) 0.5 2 mV 1 mA Load Current POWER SUPPLY Operating Voltage AVDD 2.7 3 5.5 V DRVDD 2.7 3 5.5 V Supply Current IAVDD 31.7 36.7 mA AVDD = 3 V, MODE = AVSS Power Consumption P 95 110 mW AVDD = DRVDD = 3 V, MODE = AVSS D Power-Down 4 mW STBY = AVDD, MODE and CLOCK = AVSS Gain Error Power Supply Rejection PSRR 1 % FS DYNAMIC PERFORMANCE (AIN = 0.5 dBFS) Signal-to-Noise and Distortion SINAD f = 3.58 MHz 46.4 49 dB f = 16 MHz 48 dB Effective Bits f = 3.58 MHz 7.8 Bits f = 16 MHz 7.7 Bits Signal-to-Noise SNR f = 3.58 MHz 47.8 49 dB f = 16 MHz 48 dB Total Harmonic Distortion THD f = 3.58 MHz 62 49.5 dB f = 16 MHz 58 dB Spurious Free Dynamic Range SFDR f = 3.58 MHz 66 51.4 dB f = 16 MHz 61 dB Differential Phase DP 0.2 Degree NTSC 40 IRE Mod Ramp Differential Gain DG 0.08 % REV. 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