12-Bit, 170/210 MSPS 3.3 V A/D Converter AD9430 FUNCTIONAL BLOCK DIAGRAM FEATURES SNR = 65 dB fIN = 70 MHz 210 MSPS AGND DRGND DRVDD AVDD SENSE VREF ENOB of 10.6 fIN = 70 MHz 210 MSPS (0.5 dBFS) AD9430 SFDR = 80 dBc f = 70 MHz 210 MSPS (0.5 dBFS) IN SCALABLE REFERENCE Excellent linearity: DNL = 0.3 LSB (typical) LVDS INL = 0.5 LSB (typical) OUTPUTS VIN+ ADC DATA, 12 2 output data options: TRACK- 12-BIT OVERRANGE AND-HOLD PIPELINE IN LVDS OR Demultiplexed 3.3 V CMOS outputs each 105 MSPS VIN CORE 2-PORT CMOS CMOS Interleaved or parallel data output option OUTPUTS LVDS at 210 MSPS DS+ 700 MHz full-power analog bandwidth DS SELECT CMOS DCO+ CLOCK OR LVDS On-chip reference and track-and-hold MANAGEMENT CLK+ DCO Power dissipation = 1.3 W typical 210 MSPS CLK 1.5 V input voltage range 3.3 V supply operation S1 S2 S4 S5 Output data format option Figure 1. Data sync input and data clock output provided Clock duty cycle stabilizer APPLICATIONS GENERAL DESCRIPTION Wireless and wired broadband communications The AD9430 is a 12-bit, monolithic, sampling analog-to-digital Cable reverse path converter (ADC) optimized for high performance, low power, Communications test equipment and ease of use. The product operates up to a 210 MSPS Radar and satellite subsystems conversion rate and is optimized for outstanding dynamic Power amplifier linearization performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and PRODUCT HIGHLIGHTS reference, are included on the chip to provide a complete conversion solution. 1. High performance. Maintains 65 dB SNR 210 MSPS with a 65 MHz input. The ADC requires a 3.3 V power supply and a differential 2. Low power. ENCODE clock for full performance operation. The digital Consumes only 1.3 W 210 MSPS. outputs are TTL/CMOS or LVDS compatible and support either 3. Ease of use. twos complement or offset binary format. Separate output LVDS output data and output clock signal allow interface power supply pins support interfacing with 3.3 V CMOS logic. to current FPGA technology. The on-chip reference and Two output buses support demultiplexed data up to 105 MSPS sample-and-hold provide flexibility in system design. Use rates in CMOS mode. A data sync input is supported for proper of a single 3.3 V supply simplifies system power supply output data port alignment in CMOS mode, and a data clock design. output is available for proper output data timing. In LVDS 4. Out of range (OR) feature. mode, the chip provides data at the ENCODE clock rate. The OR output bit indicates when the input signal is Fabricated on an advanced BiCMOS process, the AD9430 is beyond the selected input range. available in a 100-lead, surface-mount plastic package 5. Pin compatible with 10-bit AD9411 (LVDS only). (100 e-PAD TQFP) specified over the industrial temperature . range (40C to +85C). Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20052010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 02607-001AD9430 TABLE OF CONTENTS DC Specifications ............................................................................. 4 Analog Inputs ............................................................................. 28 AC Specifications.............................................................................. 6 Gain.............................................................................................. 28 Digital Specifications........................................................................ 7 ENCODE..................................................................................... 28 Switching Specifications .................................................................. 8 Voltage Reference ....................................................................... 28 Timing Diagrams.............................................................................. 9 Data Format Select..................................................................... 28 Absolute Maximum Ratings.......................................................... 10 I/P Timing Select........................................................................ 28 Explanation of Test Levels......................................................... 10 Timing Controls ......................................................................... 28 ESD Caution................................................................................ 10 CMOS Data Outputs.................................................................. 29 Pin Configurations and Function Descriptions ......................... 11 Crystal Oscillator........................................................................ 29 Equivalent Circuits ......................................................................... 15 Optional Amplifier..................................................................... 29 Typical Performance Characteristics ........................................... 16 Troubleshooting.......................................................................... 30 Terminology .................................................................................... 23 Evaluation Board, LVDS Mode .................................................... 36 Application Notes ........................................................................... 25 Power Connector........................................................................ 36 Theory of Operation .................................................................. 25 Analog Inputs ............................................................................. 36 Encode Input............................................................................... 25 Gain.............................................................................................. 36 Analog Input ............................................................................... 26 Clock ............................................................................................ 36 DS Inputs (DS+, DS)................................................................ 26 Voltage Reference ....................................................................... 36 CMOS Outputs ........................................................................... 26 Data Format Select..................................................................... 36 LVDS Outputs............................................................................. 27 Data Outputs............................................................................... 36 Voltage Reference ....................................................................... 27 Crystal Oscillator........................................................................ 36 Noise Power Ratio Testing (NPR) ............................................ 27 Outline Dimensions....................................................................... 42 Evaluation Board, CMOS Mode................................................... 28 Ordering Guide .......................................................................... 42 Power Connector........................................................................ 28 Rev. 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