12-Bit, 370 MSPS/500 MSPS, 1.8 V Analog-to-Digital Converter Data Sheet AD9434 FEATURES FUNCTIONAL BLOCK DIAGRAM VREF PWDN AGND AVDD SNR = 65 dBFS at f up to 250 MHz at 500 MSPS IN ENOB of 10.5 bits at f up to 250 MHz at 500 MSPS (1.0 dBFS) IN REFERENCE AD9434 SFDR = 78 dBc at f up to 250 MHz at 500 MSPS (1.0 dBFS) IN CML Integrated input buffer DRVDD DRGND VIN+ Excellent linearity TRACK-AND-HOLD VIN DNL = 0.5 LSB typical ADC 12 OUTPUT 12 CORE STAGING D11 TO D0 INL = 0.6 LSB typical LVDS LVDS at 500 MSPS (ANSI-644 levels) CLK+ CLOCK OR+ MANAGEMENT CLK 1 GHz full power analog bandwidth OR On-chip reference, no external decoupling required SERIAL PORT Low power dissipation DCO+ DCO 690 mW at 500 MSPSLVDS SDR mode 660 mW at 500 MSPSLVDS DDR mode SCLK/DFS SDIO CSB Programmable (nominal) input voltage range Figure 1. 1.18 V p-p to 1.6 V p-p, 1.5 V p-p nominal 1.8 V analog and digital supply operation Selectable output data format (offset binary, twos complement, Gray code) Clock duty cycle stabilizer Integrated data clock output with programmable clock and data alignment APPLICATIONS Fabricated on an advanced BiCMOS process, the AD9434 is Wireless and wired broadband communications available in a 56-lead LFCSP, specified over the industrial Cable reverse path temperature range (40C to +85C). This part is protected Communications test equipment under a U.S. patent. Radar and satellite subsystems Power amplifier linearization PRODUCT HIGHLIGHTS GENERAL DESCRIPTION 1. High Performance. Maintains 65 dBFS SNR at 500 MSPS with a 250 MHz input. The AD9434is a 12-bit monolithic sampling analog-to-digital 2. Low Power. converter (ADC) optimized for high performance, low power, Consumes only 660 mW at 500 MSPS. and ease of use. The part operates at up to a 500 MSPS 3. Ease of Use. conversion rate and is optimized for outstanding dynamic LVDS output data and output clock signal allow interface performance in wideband carrier and broadband systems. All to FPGA technology. The on-chip reference and sample- necessary functions, including a sample-and-hold and voltage and-hold provide flexibility in system design. Use of a reference, are included on the chip to provide a complete signal single 1.8 V supply simplifies system power supply design. conversion solution. The VREF pin can be used to monitor the 4. Serial Port Control. internal reference or provide an external voltage reference Standard serial port interface supports various product (external reference mode must be enabled through the SPI functions, such as data formatting, power-down, gain port). adjust, and output test pattern generation. The ADC requires a 1.8 V analog voltage supply and a differen- 5. The AD9434 is pin compatible with the AD9230, and can tial clock for full performance operation. The digital outputs are be substituted in many applications with minimal design LVDS (ANSI-644) compatible and support twos complement, changes. offset binary format, or Gray code. A data clock output is available for proper output data timing. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 09383-001AD9434 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 19 Applications ....................................................................................... 1 Analog Input and Voltage Reference ....................................... 19 General Description ......................................................................... 1 Clock Input Considerations ...................................................... 20 Functional Block Diagram .............................................................. 1 Power Dissipation and Power-Down Mode ........................... 21 Product Highlights ........................................................................... 1 Digital Outputs ........................................................................... 21 Revision History ............................................................................... 2 Timing.......................................................................................... 22 Specifications ..................................................................................... 3 VREF ............................................................................................ 22 DC Specifications ......................................................................... 3 AD9434 Configuration Using the SPI ..................................... 22 AC Specifications .......................................................................... 4 Using the AD9434 to Replace the AD9230 ............................ 23 Digital Specifications ................................................................... 5 Hardware Interface ..................................................................... 23 Switching Specifications .............................................................. 6 Configuration Without the SPI ................................................ 23 Timing Diagrams .......................................................................... 7 Memory Map .................................................................................. 25 Absolute Maximum Ratings ............................................................ 8 Reading the Memory Map Table .............................................. 25 Thermal Resistance ...................................................................... 8 Reserved Locations .................................................................... 25 ESD Caution .................................................................................. 8 Default Values ............................................................................. 25 Pin Configurations and Function Descriptions ........................... 9 Logic Levels ................................................................................. 25 Typical Performance Characteristics ........................................... 13 Outline Dimensions ....................................................................... 28 Equivalent Circuits ......................................................................... 18 Ordering Guide .......................................................................... 28 REVISION HISTORY 2/13Rev. A to Rev. B Changes to Table 4 ............................................................................. 6 Changes to Table 5 ............................................................................. 8 Changes to Reading the Memory Map Table Section ................. 25 5/11Rev. 0 to Rev. A Changes to General Description ..................................................... 1 Changes to Table 4, Aperture Time Values .................................... 6 Changes to Figure 32 ....................................................................... 17 Changes to Figure 42 ....................................................................... 19 Changes to Table 13, Register 10, Bits 7:0 Value, Register 14 Default Value, Register 15 Default Value, Register 17, Bit 7 Value and Register 18, Bit 4:0 Values ..................................................... 26 3/11Revision 0: Initial Version Rev. B Page 2 of 28