16-Bit, 80/100 MSPS ADC AD9446 FEATURES FUNCTIONAL BLOCK DIAGRAM 100 MSPS guaranteed sampling rate (AD9446-100) AGND AVDD1 AVDD2 DRGND DRVDD 83.6 dBFS SNR with 30 MHz input (3.8 V p-p input, 80 MSPS) DFS AD9446 82.6 dBFS SNR with 30 MHz input (3.2 V p-p input, 80 MSPS) DCS MODE BUFFER OUTPUT MODE 89 dBc SFDR with 30 MHz input (3.2 V p-p input, 80 MSPS) 16 VIN+ 2 PIPELINE CMOS T/H OR 95 dBFS 2-tone SFDR with 9.8 MHz and 10.8 MHz (100 MSPS) VIN ADC OR 32 LVDS 60 fsec rms jitter D15 TO D0 OUTPUT STAGING Excellent linearity 2 CLOCK CLK+ DNL = 0.4 LSB typical DCO AND TIMING REF CLK MANAGEMENT INL = 3.0 LSB typical 2.0 V p-p to 4.0 V p-p differential full-scale input Buffered analog inputs VREF SENSE REFT REFB LVDS outputs (ANSI-644 compatible) or CMOS outputs Figure 1. Data format select (offset binary or twos complement) Output clock available 3.3 V and 5 V supply operation Optional features allow users to implement various selectable operating conditions, including input range, data format select, APPLICATIONS and output data mode. MRI receivers Multicarrier, multimode cellular receivers The AD9446 is available in a Pb-free, 100-lead, surface-mount, Antenna array positioning plastic package (100-lead TQFP/EP) specified over the Power amplifier linearization industrial temperature range 40C to +85C. Broadband wireless Radar PRODUCT HIGHLIGHTS Infrared imaging Communications instrumentation 1. True 16-bit linearity. 2. High performance: outstanding SNR performance for GENERAL DESCRIPTION baseband IFs in data acquisition, instrumentation, The AD9446 is a 16-bit, monolithic, sampling analog-to-digital magnetic resonance imaging, and radar receivers. converter (ADC) with an on-chip track-and-hold circuit. It is 3. Ease of use: on-chip reference and high input impedance optimized for performance, small size, and ease of use. The track-and-hold with adjustable analog input range and an product operates up to a 100 MSPS, providing superior SNR for output clock simplifies data capture. instrumentation, medical imaging, and radar receivers employing baseband (<100 MHz) IF frequencies. 4. Packaged in a Pb-free, 100-lead TQFP/EP package. The ADC requires 3.3 V and 5.0 V power supplies and a low 5. Clock duty cycle stabilizer (DCS) maintains overall ADC voltage differential input clock for full performance operation. performance over a wide range of clock pulse widths. No external reference or driver components are required for many applications. Data outputs are CMOS or LVDS 6. OR (out-of-range) outputs indicate when the signal is compatible (ANSI-644 compatible) and include the means to beyond the selected input range. reduce the overall current needed for short trace distances. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05490-001AD9446 TABLE OF CONTENTS Features .............................................................................................. 1 Terminology.......................................................................................9 Applications....................................................................................... 1 Pin Configurations and Function Descriptions ......................... 10 General Description ......................................................................... 1 Equivalent Circuits......................................................................... 15 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ........................................... 16 Product Highlights ........................................................................... 1 Theory of Operation ...................................................................... 24 Revision History ............................................................................... 2 Analog Input and Reference Overview ................................... 24 Specifications..................................................................................... 3 Clock Input Considerations...................................................... 26 DC Specifications ......................................................................... 3 Power Considerations................................................................ 27 AC Specifications.......................................................................... 4 Digital Outputs ........................................................................... 27 Digital Specifications ................................................................... 6 Timing ......................................................................................... 27 Switching Specifications .............................................................. 6 Operational Mode Selection ..................................................... 28 Timing Diagrams.......................................................................... 7 Evaluation Board ............................................................................ 29 Absolute Maximum Ratings............................................................ 8 Outline Dimensions ....................................................................... 36 Thermal Resistance ...................................................................... 8 Ordering Guide .......................................................................... 36 ESD Caution.................................................................................. 8 REVISION HISTORY 10/05Revision 0: Initial Version Rev. 0 Page 2 of 36