16-Bit, 130 MSPS IF Sampling ADC AD9461 FEATURES FUNCTIONAL BLOCK DIAGRAM 130 MSPS guaranteed sampling rate AGND AVDD1 AVDD2 DRGND DRVDD 78.7 dBFS SNR/90 dBc SFDR with 10 MHz input DFS AD9461 (3.4 V p-p input, 130 MSPS) DCS MODE BUFFER 77.7 dBFS SNR with 170.3 MHz input OUTPUT MODE 16 VIN+ 2 (4.0 V p-p input, 130 MSPS) PIPELINE T/H CMOS OR VIN ADC OR 77.0 dBFS SNR/84 dBc SFDR with 170 MHz input LVDS 32 OUTPUT D15 TO D0 (3.4 V p-p input, 130 MSPS) STAGING 2 76.3 dBFS SNR/86 dBc SFDR with 225 MHz input CLK+ CLOCK DCO AND TIMING (3.4 V p-p input, 125 MSPS) REF CLK MANAGEMENT 89 dBFS two-tone SFDR with 169 MHz and 170 MHz (130 MSPS) 60 fsec rms jitter VREF SENSE REFT REFB Excellent linearity Figure 1. DNL = 0.6 LSB typical INL = 5.0 LSB typical 2.0 V p-p to 4.0 V p-p differential full-scale input Buffered analog inputs LVDS outputs (ANSI-644 compatible) or CMOS outputs Data format select (offset binary or twos complement) Output clock available APPLICATIONS MRI receivers Optional features allow users to implement various selectable Multicarrier, multimode, cellular receivers operating conditions, including input range, data format select, Antenna array positioning and output data mode. Power amplifier linearization Broadband wireless The AD9461 is available in a Pb-free, 100-lead, surface-mount, Radar plastic package (100-lead TQFP EP) specified over the industrial Infrared imaging temperature range 40C to +85C. Communications instrumentation PRODUCT HIGHLIGHTS GENERAL DESCRIPTION 1. True 16-bit linearity. The AD9461 is a 16-bit, monolithic, sampling, analog-to-digital 2. High performance: outstanding SNR performance for converter (ADC) with an on-chip track-and-hold circuit. It is baseband IFs in data acquisition, instrumentation, optimized for performance, small size, and ease of use. The magnetic resonance imaging, and radar receivers. AD9461 operates up to 130 MSPS, providing a superior signal- 3. Ease of use: on-chip reference and high input impedance to-noise ratio (SNR) for instrumentation, medical imaging, and track-and-hold with adjustable analog input range and an radar receivers using baseband (<100 MHz) and IF frequencies. output clock simplifies data capture. The ADC requires 3.3 V and 5.0 V power supplies and a low 4. Packaged in a Pb-free, 100-lead TQFP EP. voltage differential input clock for full performance operation. 5. Clock duty cycle stabilizer (DCS) maintains overall ADC No external reference or driver components are required for performance over a wide range of clock pulse widths. many applications. Data outputs are CMOS or LVDS compatible (ANSI-644 compatible) and include the means to reduce the 6. Out-of-range (OR) outputs indicate when the signal is overall current needed for short trace distances. beyond the selected input range. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06011-001AD9461 TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configurations and Function Descriptions ............................8 Functional Block Diagram .............................................................. 1 Equivalent Circuits......................................................................... 12 Applications....................................................................................... 1 Typical Performance Characteristics ........................................... 13 General Description ......................................................................... 1 Terminology.................................................................................... 16 Product Highlights ........................................................................... 1 Theory of Operation ...................................................................... 17 Revision History ............................................................................... 2 Analog Input and Reference Overview ................................... 17 Specifications..................................................................................... 3 Clock Input Considerations...................................................... 18 DC Specifications ......................................................................... 3 Power Considerations................................................................ 19 AC Specifications.......................................................................... 4 Digital Outputs ........................................................................... 20 Digital Specifications ................................................................... 5 Timing ......................................................................................... 20 Switching Specifications .............................................................. 5 Operational Mode Selection ..................................................... 20 Timing Diagrams.......................................................................... 6 Evaluation Board ............................................................................ 21 Absolute Maximum Ratings............................................................ 7 Outline Dimensions....................................................................... 28 Thermal Resistance ...................................................................... 7 Ordering Guide .......................................................................... 28 ESD Caution.................................................................................. 7 REVISION HISTORY 4/06Revision 0: Initial Version Rev. 0 Page 2 of 28