Quad Input, 10-Output, Dual DPLL/IEEE 1588 Synchronizer and Jitter Cleaner Data Sheet AD9543 FEATURES APPLICATIONS Dual DPLL synchronizes 2 kHz to 750 MHz physical layer PTP (IEEE 1588), and SyncE jitter cleanup and clocks providing frequency translation with jitter cleaning synchronization of noisy references Optical transport networks (OTN), SDH, and macro and small Complies with ITU-T G.8262 and Telcordia GR-253 cell base stations Supports Telcordia GR-1244, ITU-T G.812, G.813, G.823, OTN mapping/demapping with jitter cleaning G.824, G.825, and G.8273.2 Small base station clocking, including baseband and radio Continuous frequency monitoring and reference validation Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter for frequency deviation as low as 50 ppb cleanup, and phase transient control Both DPLLs feature a 24-bit fractional divider with 24-bit JESD204B support for analog-to-digital converter (ADC) and programmable modulus digital-to-analog converter (DAC) clocking 4 Programmable digital loop filter bandwidth: 10 Hz to 1850 Hz Cable infrastructures Two independent, programmable auxiliary NCOs (1 Hz to Carrier Ethernet 12 65,535 Hz, resolution < 1.4 10 Hz), suitable for GENERAL DESCRIPTION IEEE 1588 Version 2 servo feedback in PTP applications The AD9543 supports existing and emerging ITU standards for Automatic and manual holdover and reference switchover, the delivery of frequency, phase, and time of day over service providing zero delay, hitless, or phase buildout operation provider packet networks. Programmable priority-based reference switching with manual, automatic revertive, and automatic nonrevertive The 10 clock outputs of the AD9543 are synchronized to any modes supported one of up to four input references. The digital phase-locked 5 pairs of clock output pins with each pair useable as loops (DPLLs) reduce timing jitter associated with the external differential LVDS/HCSL/CML or as 2 single-ended outputs references. The digitally controlled loop and holdover circuitry (1 Hz to 500 MHz) continuously generate a low jitter output signal, even when all 2 differential or 4 single-ended input references reference inputs fail. Crosspoint mux interconnects reference inputs to PLLs The AD9543 is available in a 48-lead LFCSP (7 mm 7 mm) Supports embedded (modulated) input/output clock signals package and operates over the 40C to +85C temperature Fast DPLL locking modes range. Provides internal capability to combine the low phase noise of a crystal resonator or crystal oscillator with the Note that throughout this data sheet, multifunction pins, such frequency stability and accuracy of a TCXO or OCXO as SDO/M5, are referred to either by the entire pin name or by a External EEPROM support for autonomous initialization single function of the pin, for example, M5, when only that Single 1.8 V power supply operation with internal regulation function is relevant. Built in temperature monitor/alarm and temperature compensation for enhanced zero delay performance Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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AD9543 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Clock Outputs ............................................................................. 32 Applications ....................................................................................... 1 System Clock PLL ........................................................................... 33 General Description ......................................................................... 1 System Clock Input Frequency Declaration ........................... 33 Revision History ............................................................................... 3 System Clock Source .................................................................. 33 Functional Block Diagram .............................................................. 4 2 Frequency Multiplier ............................................................ 33 Specifications ..................................................................................... 5 Prescale Divider .......................................................................... 34 Supply Voltage ............................................................................... 5 Feedback Divider ........................................................................ 34 Supply Current .............................................................................. 5 System Clock PLL Output Frequency ..................................... 34 Power Dissipation ......................................................................... 5 System Clock PLL Lock Detector............................................. 34 System Clock Inputs, XOA and XOB ......................................... 6 System Clock Stability Timer .................................................... 34 Reference Inputs ........................................................................... 7 System Clock Input Termination Recommendations ........... 34 Reference Monitors ...................................................................... 8 Digital PLL (DPLL) ........................................................................ 35 DPLL Phase Characteristics ........................................................ 9 Overview ..................................................................................... 35 Distribution Clock Outputs ........................................................ 9 DPLL Phase/Frequency Lock Detectors ................................. 35 Time Duration of Digital Functions ........................................ 10 DPLL Loop Controller ............................................................... 35 Digital PLL (DPLL0, DPLL1) Specifications .......................... 11 Applications Information .............................................................. 36 Digital PLL Lock Detection Specifications ............................. 11 Optical Networking Line Card ................................................. 36 Holdover Specifications ............................................................. 12 Small Cell Base Station .............................................................. 37 Analog PLL (APLL0, APLL1) Specifications .......................... 12 IEEE 1588 Servo ......................................................................... 38 Output Channel Divider Specifications .................................. 12 Initialization Sequence................................................................... 39 Auxiliary Circuit Specifications ................................................ 13 Status and Control Pins ................................................................. 42 System Clock Compensation Specifications ........................... 13 Multifunction Pins at Reset/Power-Up ................................... 43 Temperature Sensor Specifications .......................................... 13 Status Functionality.................................................................... 43 Serial Port Specifications ........................................................... 14 Control Functionality ................................................................ 44 Logic Input Specifications (RESETB, M0 to M6) .................. 16 Interrupt Request (IRQ) ................................................................ 48 Logic Output Specifications (M0 to M6) ................................ 16 IRQ Monitor ............................................................................... 48 Jitter Generation (Random Jitter) ............................................ 17 IRQ Mask..................................................................................... 48 Phase Noise ................................................................................. 18 IRQ Clear ..................................................................................... 48 Absolute Maximum Ratings .......................................................... 21 Watchdog Timer ............................................................................. 50 Thermal Resistance .................................................................... 21 Lock Detectors ................................................................................ 51 ESD Caution ................................................................................ 21 DPLL Lock Detectors ................................................................ 51 Pin Configuration and Function Descriptions ........................... 22 Phase Step Detector ........................................................................ 53 Typical Performance Characteristics ........................................... 25 Phase Step Limit ......................................................................... 53 Terminology .................................................................................... 29 Skew Adjustment ........................................................................ 54 Theory of Operation ...................................................................... 30 EEPROM Usage .............................................................................. 55 Overview ...................................................................................... 30 Overview ..................................................................................... 55 Reference Input Physical Connections .................................... 30 EEPROM Controller General Operation ................................ 55 Input/Output Termination Recommendations .......................... 31 EEPROM Instruction Set .......................................................... 56 System Clock Inputs ................................................................... 31 Multidevice Support................................................................... 58 Reference Clock Inputs .............................................................. 31 Serial Control Port ......................................................................... 60 Rev. 0 Page 2 of 66