PCI Express/Jitter Attenuator 874002 DATA SHEET GENERAL DESCRIPTION FEATURES The 874002 is a high performance Differential-to-LVDS Jitter Two differential LVDS output pair Attenuator designed for use in PCI Express systems. In One differential clock input some PCI Express systems, such as those found in desktop CLK and nCLK supports the following input types: PCs, the PCI Express clocks are generated from a low LVPECL, LVDS, LVHSTL, SSTL, HCSL bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate Output frequency range: 98MHz - 160MHz high frequency random and deterministic jitter components Input frequency range: 98MHz - 128MHz from the PLL synthesizer and from the system board. The 874002 has 3 PLL bandwidth modes: 200kHz, 400kHz, VCO range: 490MHz - 640MHz and 800kHz. The 200kHz mode will provide maximum jitter Cycle-to-cycle jitter: 35ps (maximum) attenuation, but with higher PLL tracking skew and spread 3.3V operating supply spectrum modulation from the motherboard synthesizer may be attenuated. The 400kHz provides an intermediate band- Three bandwidth modes allow the system designer to make width that can easily track triangular spread pro les, while providing jitter attenuation/tracking skew design trade-offs good jitter attenuation. The 800kHz bandwidth provides the best 0C to 70C ambient operating temperature tracking skew and will pass most spread pro les, but the jitter attenuation will not be as good as the lower bandwidth modes. Available in lead-free (RoHS 6) package Because some 2.5Gb serdes have x20 multipliers while others have than x25 multipliers, the 874002 can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100MHz input/125MHz output) using PLL BANDWIDTH (TYPICAL) the F SEL pin. BW SEL rd TM The 874002 uses IDTs 3 Generation FemtoClock 0 = PLL Bandwidth: 200kHz PLL technology to achieve the lowest possible phase noise. Float = PLL Bandwidth: 400kHz (Default) The device is packaged in a 20 Lead TSSOP package, making it 1 = PLL Bandwidth: 800kHz ideal for use in space constrained applications such as PCI Express add-in cards. BLOCK DIAGRAM PIN ASSIGNMENT Pullup OE Pulldown F SEL Float BW SEL 0 = 200kHz Output Divider QA0 Float = 400kHz 0 5 (default) 1 = 800kHz 1 4 nQA0 Pulldown CLK Phase VCO Pullup nCLK 490 - 640 MHz Detector 874002 QA1 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm nQA1 Pulldown FB IN package body Pullup nFB IN G Package Top View 5 (fixed) FB OUT nFB OUT Pulldown MR 874002 REVISION A 7/16/15 1 2015 Integrated Device Technology, Inc.874002 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 20 nQA0, QA0 Output Differential output pair. LVDS interface levels. 2, 19 V Power Output supply pins. DDO 3, FB OUT, Output Differential feedback output pair. LVDS interface levels. 4 nFB OUT Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (Qx, FB OUT) to go low and the inverted 5 MR Input Pulldown outputs (nQx, nFB OUT) to go high. When logic LOW, the internal divid- ers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pullup/ PLL Bandwidth select input. 0 = 200kHz, Float = 400kHz, 1 = 800kHz. 6 BW SEL Input Pulldown See Table 3B. 7 nc Unused No connect. 8V Power Analog supply pin. DDA 9 F SEL Input Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C. 10 V Power Core supply pin. DD Output enable pin. When HIGH, the outputs are active. When LOW, the 11 OE Input Pullup outputs are in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A. 12 CLK Input Pulldown Non-inverting differential clock input. 13 nCLK Input Pullup Inverting differential clock input. 14 GND Power Power supply ground. 15 FB IN Input Pulldown Non-inverting differential feedback input. 16 nFB IN Input Pullup Inverting differential feedback input. 17, 18 nQA1, QA1 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN TABLE 3A. OUTPUT ENABLE FUNCTION TABLE TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL Input Outputs Input PLL Bandwidth (Typical) OE QAx/nQAx FB OUT/nFB OUT BW SEL 0 HiZ Enabled 0 200kHz 1 Enabled Enabled 1 800kHz Float 400kHz TABLE 3C. FREQUENCY SELECT FUNCTION TABLE Input Outputs F SEL QA 0:1 /nQA 0:1 FB OUT/nFB OUT 0 (default) 5 5 14 5 PCI EXPRESS/JITTER ATTENUATOR 2 REVISION A 7/16/15