DATASHEET FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER ICS342 Description Features The ICS342 is a low cost, dual-output, field programmable 8-pin SOIC package (Pb-free) clock synthesizer. The ICS342 can generate two output Highly accurate frequency generation frequencies from 250 kHz to 200 MHz, using up to two M/N Multiplier PLL: M = 1...2048, N = 1...1024 independently configurable PLLs. The outputs may employ Output clock frequencies up to 200 MHz Spread Spectrum techniques to reduce system electro-magnetic interference (EMI). Two ROM locations for frequency and spread selection TM Spread spectrum capability for lower system EMI Using IDTs VersaClock software to configure the PLL Center or Down Spread up to 4% total and output, the ICS342 contains a One-Time Programmable (OTP) ROM to allow field programmability. Selectable 32 kHz or 120 kHz modulation Programming features include 2 selectable configuration Input crystal frequency from 5 to 27 MHz registers. Using Phase-Locked Loop (PLL) techniques, the Input clock frequency from 2 to 50 MHz device runs from a standard fundamental mode, Operating voltage of 3.3 V inexpensive crystal, or clock. It can replace multiple crystals and oscillators, saving board space and cost. Advanced, low power CMOS process For one output clock, use the ICS341. For three output The device also has a power down feature that tri-states the clocks, see the ICS343. For more than three outputs, see clock outputs and turns off the PLLs when the PDTS pin is the ICS345 or ICS348. taken low. The ICS342 is also available in factory programmed custom versions for high-volume applications. Block Diagram VDD OTP ROM with PLL SEL Divider CLK1 Values PLL Clock Synthesis, Spred Spectrum and Crystal or Control Circuitry clock input X1/ICLK Crystal CLK2 Oscillator X2 External capacitors are GND required with a crystal input. PDTS (both outputs and PLL) IDT / ICS FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER 1 ICS342 REV N 090613ICS342 FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER Pin Assignment Output Clock Selection Table X1/ICLK 1 8 X2 SEL CLK1 (MHz) CLK2 (MHz) Spread Percentage VDD 2 7 PDTS 0User User User GND 3 6 SEL Configurable Configurable Configurable 1User User User CLK1 4 5 CLK2 Configurable Configurable Configurable 8-pin (150 mil) SOIC Pin Description Pin Pin Pin Pin Description Number Name Type 1 X1/ICLK XI Connect this pin to a crystal or external clock input. 2 VDD Power Connect to +3.3 V. 3 GND Power Connect to ground. 4 CLK1 Output Clock output. Weak internal pull-down when tri-state. 5 CLK2 Output Clock output. Weak internal pull-down when tri-state. 6 SEL Input Select for frequency selection on CLK1 and CLK2. Internal pull-up resistor. Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up 7PDTS Input resistor. 8 X2 XO Connect this pin to a crystal, or float for clock input. External Components capacitors must be connected from each of the pins X1 and Series Termination Resistor X2 to ground. Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly The value (in pF) of these crystal caps should equal (C -6 L used trace impedance), place a 33 resistor in series with pF)*2. In this equation, C = crystal load capacitance in pF. L the clock line, as close to the clock output pin as possible. Example: For a crystal with a 16 pF load capacitance, each The nominal impedance of the clock output is 20. crystal capacitor would be 20 pF (16-6) x 2 = 20. Decoupling Capacitor PCB Layout Recommendations As with any high-performance mixed-signal IC, the ICS342 must be isolated from system power supply noise to perform For optimum device performance and lowest output phase optimally. noise, the following guidelines should be observed. A decoupling capacitor of 0.01F must be connected 1) The 0.01F decoupling capacitor should be mounted on between VDD and the PCB ground plane. the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin should Crystal Load Capacitors be kept as short as possible, as should the PCB trace to the The device crystal connections should include pads for ground via. Distance of the ferrite bead and bulk decoupling small capacitors from X1 to ground and from X2 to ground. from the device is less critical. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load 2) The external crystal should be mounted just next to the capacitance. Because load capacitance can only be device with short traces. The X1 and X2 traces should not increased in this trimming process, it is important to keep be routed next to each other with minimum spaces, instead stray capacitance to a minimum by using very short PCB they should be separated and away from other traces. traces (and no vias) between the crystal and device. Crystal IDT / ICS FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER 2 ICS342 REV N 090613