Quad Input, 10-Output, Dual DPLL/IEEE 1588, 1 pps Synchronizer and Jitter Cleaner Data Sheet AD9545 FEATURES APPLICATIONS Dual DPLL synchronizes 1 Hz to 750 MHz physical layer Global positioning system (GPS), PTP (IEEE 1588), and clocks, providing frequency translation with jitter synchronous Ethernet (SyncE) jitter cleanup and cleaning of noisy references synchronization Complies with ITU-T G.8262 and Telcordia GR-253 Optical transport networks (OTN), synchronous digital Supports Telcordia GR-1244, ITU-T G.812, ITU-T G.813, hierarchy (SDH), and macro and small cell base stations ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2 Small base station clocking, including baseband and radio Continuous frequency monitoring and reference validation Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter 8 for frequency deviation as low as 50 ppb (5 10 ) cleanup, and phase transient control Both DPLLs feature a 24-bit fractional divider with 24-bit JESD204B support for analog-to-digital converter (ADC) and programmable modulus digital-to-analog converter (DAC) clocking 4 Programmable digital loop filter bandwidth: 10 Hz to 1850 Hz Cable infrastructures 2 independent, programmable auxiliary NCOs (1 Hz to Carrier Ethernet 12 65,535 Hz, resolution < 1.37 10 Hz), suitable for GENERAL DESCRIPTION IEEE 1588 Version 2 servo feedback in PTP applications The AD9545 supports existing and emerging International Automatic and manual holdover and reference switchover, Telecommunications Union (ITU) standards for the delivery of providing zero delay, hitless, or phase buildout operation frequency, phase, and time of day over service provider packet Programmable priority-based reference switching with networks, including ITU-G.8262, ITU-T G.812, ITU-T G.813, manual, automatic revertive, and automatic nonrevertive ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2. modes supported 5 pairs of clock output pins with each pair useable as The 10 clock outputs of the AD9545 are synchronized to any differential LVDS/HCSL/CML or as 2 single-ended outputs one of up to four input references. The digital phase-locked (1 Hz to 500 MHz) loops (DPLLs) reduce timing jitter associated with the external 2 differential or 4 single-ended input references references. The digitally controlled loop and holdover circuitry Crosspoint mux interconnects reference inputs to PLLs continuously generate a low jitter output signal, even when all Supports embedded (modulated) input/output clock signals reference inputs fail. Fast DPLL locking modes The AD9545 is available in a 48-lead LFCSP (7 mm 7 mm) Provides internal capability to combine the low phase noise package and operates over the 40C to +85C temperature range. of a crystal resonator or crystal oscillator with the frequency stability and accuracy of a TCXO or OCXO Note that throughout this data sheet, multifunction pins, such External EEPROM support for autonomous initialization as SDO/M5, are referred to either by the entire pin name or by Single 1.8 V power supply operation with internal regulation a single function of the pin, for example, M5, when only that Built in temperature monitor and alarm and temperature function is relevant. compensation for enhanced zero delay performance Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20202021 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. AD9545 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions .......................... 37 Applications ...................................................................................... 1 Typical Performance Characteristics .......................................... 39 General Description ......................................................................... 1 Terminology .................................................................................... 44 Revision History ............................................................................... 5 Theory of Operation ...................................................................... 45 Functional Block Diagram .............................................................. 8 Input/Output Termination Recommendations ......................... 46 Specifications .................................................................................... 9 System Clock Inputs .................................................................. 46 Operating Temperature ............................................................... 9 Reference Clock Inputs ............................................................. 46 Supply Voltage .............................................................................. 9 Clock Outputs ............................................................................. 47 Supply Current ............................................................................. 9 System Clock PLL ........................................................................... 49 Power Dissipation ...................................................................... 10 System Clock PLL Overview ..................................................... 49 System Clock Inputs, XOA and XOB ...................................... 11 System Clock Input Frequency Declaration .......................... 49 Reference Inputs ......................................................................... 12 System Clock Source .................................................................. 49 Reference to Reference Coupling ............................................. 14 Prescale Divider .......................................................................... 50 Reference to Mx Pin Input Timing Skew ............................... 16 Feedback Divider ....................................................................... 50 Reference Monitors .................................................................... 17 System Clock PLL Output Frequency ..................................... 50 Distribution Clock Outputs ...................................................... 18 System Clock PLL Lock Detector ............................................ 50 Output to Output Timing Skew ............................................... 21 System Clock Stability Timer ................................................... 50 Output Timing Skew Between Mx Pins and OUTxyP and/or System Clock Calibration .......................................................... 50 OUTxyN Pins ............................................................................. 22 System Clock Stability Compensation .................................... 51 Time Duration of Digital Functions ........................................ 22 Reference Clock Input Receivers ................................................. 52 DPLL0 and DPLL1 Specifications ............................................ 23 Reference Clock Receivers Overview ...................................... 52 DPLL Lock Detection Specifications ....................................... 23 Single-Ended Mode ................................................................... 52 DPLL Phase Characteristics ...................................................... 24 Differential Mode ....................................................................... 52 DPLL Propagation Delay .......................................................... 25 Reference Dividers (R-Dividers) .................................................. 54 DPLL Propagation Delay Variation ........................................ 25 Reference Monitor ......................................................................... 55 Holdover Specifications............................................................. 26 Reference Monitor Overview ................................................... 55 Analog PLL (APLL0 and APLL1) Specifications ................... 26 Reference Monitor State Machine ........................................... 56 Output Channel Divider Specifications .................................. 26 Reference Monitor Controls ..................................................... 56 Auxiliary Circuit Specifications ............................................... 27 Monitor Time Base .................................................................... 58 Mx to Mx Pin Output Timing Skew ........................................ 27 Reference Period Jitter Estimation .......................................... 58 System Clock Compensation Specifications .......................... 28 Reference Monitor Decision Time .......................................... 58 Temperature Sensor Specifications ......................................... 28 Reference Validation ................................................................. 58 Logic Input Specifications (RESETB, M0 to M6 Pins) ......... 28 Reference Monitor Reset ........................................................... 59 Logic Output Specifications (M0 to M6 Pins) ....................... 29 Reference Demodulator ................................................................ 60 Serial Port Specifications ........................................................... 30 Reference Demodulator Overview .......................................... 60 Jitter Generation (Random Jitter) ............................................ 32 Demodulator Enable .................................................................. 60 Phase Noise ................................................................................. 33 Demodulator Delay ................................................................... 61 Absolute Maximum Ratings ......................................................... 36 Demodulator Polarity ................................................................ 61 Thermal Resistance .................................................................... 36 Automatic Polarity Detection .................................................. 61 ESD Caution................................................................................ 36 Demodulator Sensitivity ........................................................... 61 Rev. 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