Dual PLL Precision Synthesizer Data Sheet AD9578 FEATURES GENERAL DESCRIPTION Any output frequency precision synthesis The AD9578 is a programmable synthesizer intended for jitter 11.8 MHz to 919 MHz attenuation and asynchronous clocking applications in high Better than 0.1 ppb frequency resolution performance telecommunications, networking, data storage, Ultralow rms jitter (12 kHz to 20 MHz) serializer/deserializer (SERDES), and physical layer (PHY) <300 fs rms using integer synthesis applications. The device incorporates two low jitter PLLs that <405 fs rms using fractional synthesis provide any frequency with precision better than 0.1 ppb, each Dual reference inputs support LVPECL, LVDS, 1.8 V LVCMOS, with two separate output dividers, for a total of four programmable or fundamental mode AT cut crystals from 22 MHz to outputs, delivering maximum flexibility and jitter performance. 54 MHz or reference clocks from 20 MHz to 60 MHz Each output is independently programmable to provide frequen- Numerical (NCO) frequency control cies of up to 919 MHz with <410 fs typical rms jitter (12 kHz to Dynamically pullable output frequency enables FPGA- 20 MHz) utilizing compact, low cost fundamental mode crystals based PLLs (HDL available) (XTALs) that enable a robust supply chain. Using integer Fast serial peripheral interface (SPI) bus write speeds up to frequency synthesis, the AD9578 is capable of achieving rms 100 MHz jitter as low as 290 fs. On-the-fly frequency changes The AD9578 is packaged with a factory programmed default Dual PLL in compact 7 mm 7 mm package power-on configuration. After power-on, all settings including Replaces multiple large clock ICs, PLLs, fanout buffers, output frequency are reconfigurable through a fast SPI. crystal oscillators (XOs), and voltage controlled crystal oscillators (VCXOs) The AD9578 architecture permits it to be used as a numerically Mix and match output buffers controlled oscillator (NCO). This allows the user to dynamically In-circuit programmable LVPECL/LVDS/HCSL/LVCMOS change the frequency using the fast SPI bus. FPGAs and other Independent buffer (VDDOx) drives multiple technologies devices can take advantage of this function to implement digital Enhanced power supply noise rejection PLLs with configurable loop bandwidths for jitter attenuation applications, precision disciplined clocks that lock to tight APPLICATIONS stability references, or digitally controlled precision timing FPGA-based jitter attenuators and low jitter PLLs applications, such as network timing and IEEE 1588 applications. Precision disciplined clocks and clock synthesizers The SPI bus can operate up to 50 MHz, enabling fast FPGA Multirate clock synthesizers loops while multiple devices share the same bus. The AD9578 Optical: OTN/SDH/SONET can also be used in multirate precision applications, such as Broadcast video: 3G SDI, HD SDI, SDI broadcast video or OTN. HDL FPGA code for digital PLL Networking and storage: Ethernet/SAS/Fibre Channel applications is available from Analog Devices, Inc. Wireless infrastructure: OBSAI/CPRI Industrial: IEEE 1588 Numerically controlled oscillators (NCOs) SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM REFOUT, OPTIONAL AD9578 REFOUT XO4 OUT1, DIVIDER REF2 OUT1 FRACTIONAL PLL1 OUT2, REF XO3 DIVIDER OUT2 INPUT MUX OUT3, OPTIONAL DIVIDER OUT3 FRACTIONAL XO2 PLL2 OUT4, REF1 DIVIDER OUT4 XO1 SPI AND OTP OUTPUT POWER ENABLE PROGRAMMABLE SUPPLIES LOGIC LOGIC CONTROL NOTES 1. IF SUPPLYING A SINGLE-ENDED 1.8V CMOS SIGNAL, CONNECT THE SIGNAL TO EITHER XO2 OR XO4. Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 11356-001AD9578 Data Sheet TABLE OF CONTENTS Features .....................................................................................1 Overview ............................................................................. 25 Applications...............................................................................1 Crystal Oscillator Gain ........................................................ 25 General Description ..................................................................1 Crystal Load Capacitors....................................................... 25 Simplified Functional Block Diagram........................................1 PLLs ........................................................................................ 26 Revision History ........................................................................3 Overview ............................................................................. 26 Specifications .............................................................................4 PLL Modes of Operation ..................................................... 26 Supply Voltage and Current (2.5 V Operation) ......................4 VCO .................................................................................... 27 Supply Voltage and Current (3.3 V Operation) ......................4 Charge Pump....................................................................... 27 Power Dissipation ..................................................................4 Output Dividers................................................................... 27 Logic Inputs ( , , OEREF, OE1, OE2, OE3, OE4) .........5 Loss of Lock Indicator ......................................................... 27 CS PD1 Resets................................................................................... 27 Reference Inputs (XO1, XO2, XO3, XO4) ..............................5 Example Values for 49.152 MHz crystal .............................. 28 Distribution Clock Outputs (Including REFOUT/ ) 6 REFOUT SPI Programming .................................................................... 29 Serial Port ..............................................................................9 Overview ............................................................................. 29 Digital PLL...........................................................................10 SPI Description.................................................................... 29 Digital Functions Timing.....................................................10 OTP Programming .............................................................. 30 Jitter Generation Using 49.152 MHz Crystal........................10 Register Map ........................................................................... 32 Jitter Generation Using 25 MHz Square wave ......................11 Register Map Bit Descriptions ................................................. 34 Absolute Maximum Ratings ....................................................12 Chip and Manufacturer ID (Register 0, Address 0x00)........ 34 ESD Caution ........................................................................12 Product ID, Chip ID, and User Programing Space (Register 1, Pin Configuration and Function Descriptions.........................13 Address 0x01) ...................................................................... 34 Typical Performance Characteristics .......................................15 External Pin Readback and Override (Register 2, Address Test Setup and Configuration Circuits.....................................18 0x02).................................................................................... 34 Input/Output Termination Recommendations ........................19 REFOUT/OUTPUT Divider Enable (Register 3, Address Getting Started.........................................................................20 0x03).................................................................................... 36 Chip Power Monitor and Startup .........................................20 XTAL1 and Output Buffer Configuration (Register 4, Address 0x04) ...................................................................... 37 Device Register Programming Using a Register Setup File ..20 Output Driver Configuration (Register 5, Address 0x05) .... 38 OTP Programming ..............................................................20 PLL1 Configuration (Register 6, Address 0x06) .................. 38 Theory of Operation................................................................21 PLL1 Configuration (Register 7, Address 0x07) .................. 39 Overview..............................................................................21 PLL2 Configuration (Register 8, Address 0x08) .................. 40 PLL and Output Driver Control ..............................................22 PLL2 Configuration (Register 9, Address 0x09) .................. 40 Overview..............................................................................22 XTAL2 Configuration (Register 10, Address 0x0A)............. 42 PLL Enable/Disable..............................................................22 Reserved (Register 11, Address 0x0B).................................. 42 Output Driver Format..........................................................23 PLL1 K Band (Register 12, Address 0x0C)...................... 42 VCO Output Configuration Example ...........................................23 Reserved (Register 13, Address 0x0D) ................................. 42 Reference Input........................................................................24 PLL2 K Band (Register 14, Address 0x0E) ...................... 43 VCO Overview..............................................................................24 PLL Lock Detect (Register 15, Address 0x0F)...................... 43 Reference Input ....................................................................24 Outline Dimensions ................................................................ 44 Crystal Oscillator Amplifier Enable .....................................24 Ordering Guide ................................................................... 44 REFOUT/REFOUT Source Selection...................................24 Crystal Oscillator Inputs..........................................................25 Rev. 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