Dual, 12-Bit, 80 MSPS/125 MSPS, Serial LVDS 1.8 V Analog-to-Digital Converter Data Sheet AD9635 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD 1.8 V supply operation Low power: 115 mW per channel at 125 MSPS with scalable D0A+ AD9635 power options D0A 12 VINA+ 12-BIT PIPELINE D1A+ SNR = 71 dBFS (to Nyquist) ADC VINA D1A SFDR = 93 dBc at 70 MHz 12 D0B+ VCM DNL = 0.1 LSB to +0.2 LSB (typical) INL = 0.4 LSB (typical) D0B Serial LVDS (ANSI-644, default) and low power, reduced 12 D1B+ VINB+ 12-BIT PIPELINE range option (similar to IEEE 1596.3) ADC D1B VINB 650 MHz full power analog bandwidth DCO+ 12 2 V p-p input voltage range DCO REFERENCE Serial port control FCO+ FCO Full chip and individual channel power-down modes Flexible bit orientation SERIAL PORT 1 TO 8 Built-in and custom digital test pattern generation INTERFACE CLOCK DIVIDER Clock divider Programmable output clock and data alignment SCLK/ SDIO/ CSB CLK+ CLK Programmable output resolution DFS PDWN Standby mode Figure 1. APPLICATIONS The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for Communications capturing data on the output and a frame clock output (FCO) for Diversity radio systems signaling a new output byte are provided. Individual channel Multimode digital receivers power-down is supported the AD9635 typically consumes less GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA than 2 mW in the full power-down state. The ADC provides I/Q demodulation systems several features designed to maximize flexibility and minimize Smart antenna systems system cost, such as programmable output clock and data align- Broadband data applications ment and digital test pattern generation. The available digital Battery-powered instruments test patterns include built-in deterministic and pseudorandom Handheld scope meters Portable medical imaging and ultrasound patterns, along with custom user-defined test patterns entered via Radar/LIDAR the serial port interface (SPI). The AD9635 is available in a RoHS-compliant, 32-lead LFCSP. GENERAL DESCRIPTION It is specified over the industrial temperature range of 40C The AD9635 is a dual, 12-bit, 80 MSPS/125 MSPS analog-to- to +85C. digital converter (ADC) with an on-chip sample-and-hold circuit PRODUCT HIGHLIGHTS designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS 1. Small Footprint. Two ADCs are contained in a small, space- and is optimized for outstanding dynamic performance and low saving package. power in applications where a small package size is critical. 2. Low Power. The AD9635 uses 115 mW/channel at 125 MSPS with scalable power options. The ADC requires a single 1.8 V power supply and LVPECL-/ 3. Pin Compatibility with the AD9645, a 14-Bit Dual ADC. CMOS-/LVDS-compatible sample rate clock for full performance 4. Ease of Use. A data clock output (DCO) operates at operation. No external reference or driver components are frequencies of up to 500 MHz and supports double data required for many applications. rate (DDR) operation. 5. User Flexibility. SPI control offers a wide range of flexible features to meet specific system requirements. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20122015 Analog Devices, Inc. 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PLL, SERIALIZER AND DDR LVDS DRIVERS 10577-001AD9635 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power Dissipation and Power-Down Mode ........................... 22 Applications ....................................................................................... 1 Digital Outputs and Timing ..................................................... 23 General Description ......................................................................... 1 Output Test Modes ..................................................................... 26 Functional Block Diagram .............................................................. 1 Serial Port Interface (SPI) .............................................................. 27 Product Highlights ........................................................................... 1 Configuration Using the SPI ..................................................... 27 Revision History ............................................................................... 2 Hardware Interface ..................................................................... 28 Specifications ..................................................................................... 3 Configuration Without the SPI ................................................ 28 DC Specifications ......................................................................... 3 SPI Accessible Features .............................................................. 28 AC Specifications .......................................................................... 4 Memory Map .................................................................................. 29 Digital Specifications ................................................................... 5 Reading the Memory Map Register Table ............................... 29 Switching Specifications .............................................................. 6 Memory Map Register Table ..................................................... 30 Timing Specifications .................................................................. 6 Memory Map Register Descriptions ........................................ 33 Absolute Maximum Ratings .......................................................... 10 Applications Information .............................................................. 35 Thermal Resistance .................................................................... 10 Design Guidelines ...................................................................... 35 ESD Caution ................................................................................ 10 Power and Ground Guidelines ................................................. 35 Pin Configuration and Function Descriptions ........................... 11 Clock Stability Considerations ................................................. 35 Typical Performance Characteristics ........................................... 12 Exposed Pad Thermal Heat Slug Recommendations ............ 35 AD9635-80 ................................................................................... 12 VCM ............................................................................................. 35 AD9635-125 ................................................................................. 15 Reference Decoupling ................................................................ 35 Equivalent Circuits ......................................................................... 18 SPI Port ........................................................................................ 35 Theory of Operation ...................................................................... 19 Outline Dimensions ....................................................................... 36 Analog Input Considerations .................................................... 19 Ordering Guide .......................................................................... 36 Voltage Reference ....................................................................... 20 Clock Input Considerations ...................................................... 21 REVISION HISTORY 10/15Rev. A to Rev. B Changes to Pin 21 Description ..................................................... 11 Changed tSAMPLE/16 to tSAMPLE/12, AD9516 to AD9516-0/ Changes to Voltage Reference Section ......................................... 20 AD9516-1/AD9516-2/AD9516-3/AD9516-4/AD9516-5, Changes to Table 11 ....................................................................... 25 and AD9517 to AD9517-0/AD9517-1/AD9517-2/AD9517-3/ Changes to First Paragraph of Serial Port Interface (SPI) AD9517-4 ....................................................................... Throughout Section .............................................................................................. 27 Changes to General Description Section ...................................... 1 Changes to SPI Accessible Features Section ............................... 28 Added Endnote 4, Table 4 ............................................................... 6 Changes to Output Phase (Register 0x16) Bits 6:4 Input Changes to Digital Outputs and Timing Section ....................... 25 Clock Phase Adjust Section........................................................... 33 Changes to Resolution/Sample Rate Override (Register 0x100) 8/14Rev. 0 to Rev. A Section and User I/O Control 3 (Register 0x102) Bit 3VCM Added Propagation Delay Parameters of 1.5 ns (min) Power-Down Section ..................................................................... 34 and 3.1 ns (max), Table 4 ................................................................. 6 Added Clock Stability Considerations Section ........................... 35 Changes to Figure 2 and Figure 3 ................................................... 7 Changes to Figure 4 and Figure 5 ................................................... 8 6/12Revision 0: Initial Version Rev. B Page 2 of 36