14-Bit, 80 MSPS/155 MSPS, 1.8 V Serial Output Analog-to-Digital Converter (ADC) Data Sheet AD9641 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD SDIO SCLK CSB DRVDD JESD204A coded serial digital outputs SNR = 73.7 dBFS at 70 MHz/80 MSPS SPI AD9641 SNR = 72.8 dBFS at 70 MHz and 155 MSPS SFDR = 94 dBc at 70 MHz and 80 MSPS PROGRAMMING DATA SFDR = 90 dBc at 70 MHz and 155 MSPS DOUT+ Low power: 238 mW at 80 MSPS, 313 mW at 155 MSPS VIN+ DOUT 1.8 V supply operation ADC DSYNC+ VIN Integer 1-to-8 input clock divider DSYNC VCM IF sampling frequencies to 250 MHz REFERENCE DATA RATE 148.6 dBFS/Hz input noise at 180 MHz and 80 MSPS MULTIPLIER 148.1 dBFS/Hz input noise at 180 MHz and 155 MSPS DUTY CYCLE Programmable internal ADC voltage reference STABILIZER Flexible analog input range: 1.4 V p-p to 2.1 V p-p DIVIDE-BY-1 CLK+ MULTICHIP ADC clock duty cycle stabilizer (DCS) TO SYNC DIVIDE-BY-8 CLK Serial port control User-configurable, built-in self-test (BIST) capability AGND SYNC PDWN DRGND Energy-saving power-down modes Figure 1. APPLICATIONS The ADC output data is routed directly to the JESD204A serial Communications output port. This output is at CML voltage levels. A CMOS or Diversity radio systems LVDS synchronization input (DSYNC) is provided. Multimode digital receivers (3G and 4G) The flexible power-down options allow significant power savings, GSM, EDGE, W-CDMA, LTE, when desired. CDMA2000, WiMAX, TD-SCDMA Programming for setup and control is accomplished using a 3-wire Smart antenna systems SPI-compatible serial interface. General-purpose software radios Broadband data applications The AD9641 is available in a 32-lead LFCSP and is specified over Ultrasound equipment the industrial temperature range of 40C to +85C. GENERAL DESCRIPTION This product is protected by a U.S. patent. The AD9641 is a 14-bit, 80 MSPS/155 MSPS analog-to-digital PRODUCT HIGHLIGHTS converter (ADC) with a high speed serial output interface. The 1. An on-chip PLL allows users to provide a single ADC AD9641 is designed to support communications applications sampling clock. The PLL multiplies the ADC sampling clock where high performance, combined with low cost, small size, and to produce the corresponding JESD204A data rate clock. versatility, is desired. The JESD204A high speed serial interface 2. The configurable JESD204A output block coded data rate reduces board routing requirements and lowers pin count supports up to 1.6 Gbps. requirements for the receiving device. 3. A proprietary differential input maintains excellent SNR The ADC core features a multistage, differential pipelined performance for input frequencies of up to 250 MHz. architecture with integrated output error correction logic. The 4. Operation is from a single 1.8 V power supply. ADC features wide bandwidth, differential sample-and-hold, 5. The standard serial port interface (SPI) supports various analog input amplifiers that support a variety of user-selectable product features and functions, such as data formatting input ranges. An integrated voltage reference eases the design (offset binary, twos complement, or Gray coding), control- considerations. A duty cycle stabilizer (DCS) is provided to ling the clock DCS, power-down, test modes, voltage compensate for variations in the ADC clock duty cycle, reference mode, and serial output configuration. allowing the converter to maintain excellent performance. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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DATA SERIALIZER, ENCODER, AND CML DRIVERS 09210-001AD9641 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference ....................................................................... 19 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 19 General Description ......................................................................... 1 Chip Synchronization ................................................................ 20 Functional Block Diagram .............................................................. 1 Power Dissipation and Standby Mode .................................... 21 Product Highlights ........................................................................... 1 Digital Outputs ........................................................................... 21 Revision History ............................................................................... 2 Built-In Self-Test (BIST) and Output Test .................................. 25 Specifications ..................................................................................... 3 Built-In Self-Test (BIST) ............................................................ 25 ADC DC Specifications ............................................................... 3 Output Test Modes ..................................................................... 25 ADC AC Specifications ............................................................... 4 Serial Port Interface (SPI) .............................................................. 27 Digital Specifications ................................................................... 5 Configuration Using the SPI ..................................................... 27 Switching Specifications .............................................................. 6 Hardware Interface ..................................................................... 28 Timing Specifications .................................................................. 7 SPI Accessible Features .............................................................. 28 Absolute Maximum Ratings ............................................................ 8 Memory Map .................................................................................. 29 Thermal Characteristics .............................................................. 8 Reading the Memory Map Register Table ............................... 29 ESD Caution .................................................................................. 8 Memory Map Register Table ..................................................... 29 Pin Configuration and Function Descriptions ............................. 9 Memory Map Register Descriptions ........................................ 32 Typical Performance Characteristics ........................................... 10 Applications Information .............................................................. 35 Equivalent Circuits ......................................................................... 16 Design Guidelines ...................................................................... 35 Theory of Operation ...................................................................... 17 Outline Dimensions ....................................................................... 36 ADC Architecture ...................................................................... 17 Ordering Guide .......................................................................... 36 Analog Input Considerations .................................................... 17 REVISION HISTORY 1/12Rev. A to Rev. B Added Figure 23 to Figure 40 Renumbered Sequentially ........ 13 Change to General Description Section ........................................ 1 Changes to Clock Input Considerations Section ....................... 19 Changes to Table 2 ............................................................................ 4 Changes to Digital Outputs and Timing Section ....................... 23 Moved Figure 65 and Figure 66 .................................................... 23 8/11Rev. 0 to Rev. A Added Figure 68 ............................................................................. 24 Added Model -155 ......................................................... Throughout Changes to Output Test Modes Section ...................................... 25 Changes to Features .......................................................................... 1 Changes to SPI Accessible Features Section ............................... 28 Changes to Table 1 ............................................................................ 3 Changes to Addr (Hex) 0x02, Table 17 ........................................ 29 Changes to Table 2 ............................................................................ 4 Changes to Ordering Guide .......................................................... 36 Changes to Table 4 ............................................................................ 6 Changes to Figure 11 to Figure 14 Captions ............................... 11 7/10Revision 0: Initial Version Rev. B Page 2 of 36