16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) Data Sheet AD9650 FEATURES FUNCTIONAL BLOCK DIAGRAM SDIO/ SCLK/ 1.8 V analog supply operation AVDD CSB DRVDD DCS DFS 1.8 V CMOS or LVDS output supply SPI SNR AD9650 82 dBFS at 30 MHz input and 105 MSPS data rate ORA PROGRAMMING DATA 83 dBFS at 9.7 MHz input and 25 MSPS data rate D15A (MSB) VIN+A 16 SFDR CMOS/LVDS ADC TO OUTPUT BUFFER VINA 90 dBc at 30 MHz input and 105 MSPS data rate D0A (LSB) 95 dBc at 9.7 MHz input and 25 MSPS data rate CLK+ DIVIDE 1 VREF Low power TO 8 CLK SENSE 328 mW per channel at 105 MSPS DCOA DUTY CYCLE DCO 119 mW per channel at 25 MSPS REF STABILIZER GENERATION DCOB VCM SELECT Integer 1-to-8 input clock divider IF sampling frequencies to 300 MHz RBIAS ORB D15B (MSB) Analog input range of 2.7 V p-p VINB 16 CMOS/LVDS TO ADC OUTPUT BUFFER Optional on-chip dither VIN+B D0B (LSB) Integrated ADC sample-and-hold inputs MULTICHIP SYNC Differential analog inputs with 500 MHz bandwidth ADC clock duty cycle stabilizer AGND SYNC PDWN OEB NOTES APPLICATIONS 1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY SEE FIGURE 7 FOR LVDS PIN NAMES. Industrial instrumentation Figure 1. X-Ray, MRI, and ultrasound equipment Flexible power-down options allow significant power savings, High speed pulse acquisition when desired. Chemical and spectrum analysis Direct conversion receivers Programming for setup and control is accomplished using a 3-wire Multimode digital receivers SPI-compatible serial interface. Smart antenna systems The AD9650 is available in a 64-lead LFCSP and is specified over General-purpose software radios the industrial temperature range of 40C to +85C. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9650 is a dual, 16-bit, 25 MSPS/65 MSPS/80 MSPS/ 1. On-chip dither option for improved SFDR performance 105 MSPS analog-to-digital converter (ADC) designed for with low power analog input. digitizing high frequency, wide dynamic range signals with 2. Proprietary differential input that maintains excellent SNR input frequencies of up to 300 MHz. performance for input frequencies up to 300 MHz. The dual ADC core features a multistage, differential pipelined 3. Operation from a single 1.8 V supply and a separate digital architecture with integrated output error correction logic. Each output driver supply accommodating 1.8 V CMOS or ADC features wide bandwidth, differential sample-and-hold LVDS outputs. analog input amplifiers, and shared integrated voltage reference, 4. Standard serial port interface (SPI) that supports various which eases design considerations. A duty cycle stabilizer is product features and functions, such as data formatting provided to compensate for variations in the ADC clock duty (offset binary, twos complement, or gray coding), enabling cycle, allowing the converters to maintain excellent performance. the clock DCS, power-down, and test modes. 5. Pin compatible with the AD9268 and other dual families, The ADC output data can be routed directly to the two external AD9269, AD9251, AD9231, and AD9204. This allows a 16-bit output ports or multiplexed on a single 16-bit bus. These simple migration across resolutions and bandwidth. outputs can be set to either 1.8 V CMOS or LVDS. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20102014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 08919-001AD9650 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ADC Architecture ...................................................................... 29 Applications ....................................................................................... 1 Analog Input Considerations ................................................... 29 General Description ......................................................................... 1 Voltage Reference ....................................................................... 32 Functional Block Diagram .............................................................. 1 Channel/Chip Synchronization ................................................ 34 Product Highlights ........................................................................... 1 Power Dissipation and Standby Mode .................................... 34 Revision History ............................................................................... 2 Digital Outputs ........................................................................... 35 Specifications ..................................................................................... 3 Timing.......................................................................................... 35 ADC DC Specifications ............................................................... 3 Built-In Self-Test (BIST) and Output Test .................................. 36 ADC AC Specifications ................................................................. 4 Built-In Self-Test (BIST) ............................................................ 36 Digital Specifications ................................................................... 5 Output Test Modes ..................................................................... 36 Switching Specifications ................................................................ 7 Serial Port Interface (SPI) .............................................................. 37 Timing Specifications .................................................................. 8 Configuration Using the SPI ..................................................... 37 Absolute Maximum Ratings .......................................................... 10 Hardware Interface ..................................................................... 38 Thermal Characteristics ............................................................ 10 Configuration Without the SPI ................................................ 38 ESD Caution ................................................................................ 10 SPI Accessible Features .............................................................. 38 Pin Configurations and Function Descriptions ......................... 11 Memory Map .................................................................................. 39 Typical Performance Characteristics ........................................... 15 Reading the Memory Map Register Table ............................... 39 AD9650-25 .................................................................................. 15 Memory Map Register Table ..................................................... 40 AD9650-65 .................................................................................. 18 Memory Map Register Descriptions ........................................ 42 AD9650-80 .................................................................................. 21 Applications Information .............................................................. 43 AD9650-105 ................................................................................ 24 Design Guidelines ...................................................................... 43 Equivalent Circuits ......................................................................... 28 Outline Dimensions ....................................................................... 44 Theory of Operation ...................................................................... 29 Ordering Guide .......................................................................... 44 REVISION HISTORY 12/14Rev. A to Rev. B Changes to Figure 83 ....................................................................... 32 Changes to Table 16 ........................................................................ 38 Deleted Register 0x10 Table 17 .................................................... 41 Updated Outline Dimensions ....................................................... 44 11/11Rev. 0 to Rev. A Changes to Table 17 ........................................................................ 40 7/10Revision 0: Initial Version Rev. B Page 2 of 44