14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter Data Sheet AD9680 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 AVDD3 AVDD1 SR DVDD DRVDD SPIVDD JESD204B (Subclass 1) coded serial digital outputs (1.25V) (2.5V) (3.3V) (1.25V) (1.25V) (1.25V) (1.8V TO 3.3V) 1.65 W total power per channel at 1 GSPS (default settings) BUFFER SFDR at 1 GSPS = 85 dBFS at 340 MHz, 80 dBFS at 1 GHz VIN+A ADC 14 CORE SNR at 1 GSPS = 65.3 dBFS at 340 MHz (AIN = 1.0 dBFS), VINA DDC 60.5 dBFS at 1 GHz (AIN = 1.0 dBFS) FD A SERDOUT0 4 SIGNAL SERDOUT1 ENOB = 10.8 bits at 10 MHz MONITOR SERDOUT2 SERDOUT3 DNL = 0.5 LSB FD B 14 DDC INL = 2.5 LSB VIN+B ADC CORE Noise density = 154 dBFS/Hz at 1 GSPS VINB BUFFER 1.25 V, 2.5 V, and 3.3 V dc supply operation CONTROL REGISTERS V 1P0 No missing codes FAST DETECT Internal ADC voltage reference SIGNAL SYNCINB JESD204B MONITOR Flexible input range: 1.46 V p-p to 1.94 V p-p SUBCLASS 1 CLOCK CONTROL GENERATION SYSREF AD9680-1250: 1.58 V p-p nominal AD9680-1000 and AD9680-820: 1.70 V p-p nominal CLK+ CLK 2 SPI CONTROL AD9680-500: 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal) PDWN/ 4 STBY AD9680 8 Programmable termination impedance 400 , 200 , 100 , and 50 differential AGND DRGND DGND SDIO SCLK CSB 2 GHz usable analog input full power bandwidth Figure 1. 95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation PRODUCT HIGHLIGHTS 2 integrated wideband digital processors per channel 1. Wide full power bandwidth supports IF sampling of signals 12-bit NCO, up to 4 half-band filters up to 2 GHz. Differential clock input 2. Buffered inputs with programmable input termination eases Integer clock divide by 1, 2, 4, or 8 filter design and implementation. Flexible JESD204B lane configurations 3. Four integrated wideband decimation filters and numerically Small signal dither controlled oscillator (NCO) blocks supporting multiband APPLICATIONS receivers. Communications 4. Flexible serial port interface (SPI) controls various product Diversity multiband, multimode digital receivers features and functions to meet specific system requirements. 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE 5. Programmable fast overrange detection. General-purpose software radios 6. 9 mm 9 mm, 64-lead LFCSP. Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers Rev. 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Technical Support www.analog.com FAST DETECT JESD204B HIGH SPEED SERIALIZER Tx OUTPUTS 11752-001AD9680 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 FIR Filters General Description ............................................... 58 Applications ....................................................................................... 1 Half-Band Filters ........................................................................ 59 Functional Block Diagram .............................................................. 1 DDC Gain Stage ......................................................................... 61 Product Highlights ........................................................................... 1 DDC Complex to Real Conversion ......................................... 61 Revision History ............................................................................... 3 DDC Example Configurations ................................................. 62 General Description ......................................................................... 5 Digital Outputs ............................................................................... 65 Specifications ..................................................................................... 6 Introduction to the JESD204B Interface ................................. 65 DC Specifications ......................................................................... 6 JESD204B Overview .................................................................. 65 AC Specifications .......................................................................... 7 Functional Overview ................................................................. 66 Digital Specifications ................................................................... 9 JESD204B Link Establishment ................................................. 67 Switching Specifications ............................................................ 10 Physical Layer (Driver) Outputs .............................................. 68 Timing Specifications ................................................................ 11 JESD204B Tx Converter Mapping ........................................... 71 Absolute Maximum Ratings .......................................................... 13 Configuring the JESD204B Link .............................................. 73 Thermal Characteristics ............................................................ 13 Deterministic Latency .................................................................... 76 ESD Caution ................................................................................ 13 Subclass 0 Operation .................................................................. 76 Pin Configuration and Function Descriptions ........................... 14 Subclass 1 Operation .................................................................. 76 Typical Performance Characteristics ........................................... 16 Multichip Synchronization............................................................ 78 AD9680-1250 .............................................................................. 16 Normal Mode .............................................................................. 78 AD9680-1000 .............................................................................. 20 Timestamp Mode ....................................................................... 78 AD9680-820 ................................................................................ 25 SYSREF Input ........................................................................... 80 AD9680-500 ................................................................................ 30 SYSREF Setup/Hold Window Monitor ................................. 82 Equivalent Circuits ......................................................................... 34 Latency ............................................................................................. 84 Theory of Operation ...................................................................... 36 End to End Total Latency .......................................................... 84 ADC Architecture ....................................................................... 36 Example Latency Calculation ................................................... 84 Analog Input Considerations.................................................... 36 Test Modes ....................................................................................... 85 Voltage Reference ....................................................................... 42 ADC Test Modes ........................................................................ 85 Clock Input Considerations ...................................................... 43 JESD204B Block Test Modes..................................................... 86 ADC Overrange and Fast Detect .................................................. 45 Serial Port Interface ........................................................................ 88 ADC Overrange .......................................................................... 45 Configuration Using the SPI ..................................................... 88 Fast Threshold Detection (FD A and FD B) ......................... 45 Hardware Interface ..................................................................... 88 Signal Monitor ................................................................................ 46 SPI Accessible Features .............................................................. 88 SPORT Over JESD204B ............................................................. 47 Memory Map .................................................................................. 89 Digital Downconverter (DDC) ..................................................... 49 Reading the Memory Map Register Table ............................... 89 DDC I/Q Input Selection .......................................................... 49 Memory Map Register Table ..................................................... 90 DDC I/Q Output Selection ....................................................... 49 Applications Information ............................................................ 104 DDC General Description ........................................................ 49 Power Supply Recommendations ........................................... 104 Frequency Translation.................................................................... 55 Exposed Pad Thermal Heat Slug Recommendations .......... 104 Frequency Translation General Description .............................. 55 AVDD1 SR (Pin 57) and AGND (Pin 56 and Pin 60) ............ 104 DDC NCO Plus Mixer Loss and SFDR ................................... 56 Outline Dimensions ..................................................................... 105 Numerically Controlled Oscillator........................................... 56 Ordering Guide ........................................................................ 105 FIR Filters ........................................................................................ 58 Rev. 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