14-Bit, 2.0 GSPS/2.6 GSPS, JESD204B, Dual Analog-to-Digital Converter Data Sheet AD9689 FEATURES 0.975 V, 1.9 V, and 2.5 V dc supply operation 9 GHz analog input full power bandwidth (3 dB) JESD204B (Subclass 1) coded serial digital outputs Amplitude detect bits for efficient AGC implementation Support for lane rates up to 16 Gbps per lane Programmable FIR filters for analog channel loss equalization Noise density 2 integrated, wideband digital processors per channel 152 dBFS/Hz at 2.56 GSPS at full-scale voltage = 1.7 V p-p 48-bit NCO 154 dBFS/Hz at 2.56 GSPS at full-scale voltage = 2.0 V p-p Programmable decimation rates 154.2 dBFS/Hz at 2.0 GSPS at full-scale voltage = 1.7 V p-p Phase coherent NCO switching 155.3 dBFS/Hz at 2.0 GSPS at full-scale voltage = 2.0 V p-p Up to 4 channels available 1.55 W total power per channel at 2.56 GSPS (default settings) Serial port control SFDR at 2.56 GSPS encode Supports 100 MHz SPI writes and 50 MHz SPI reads 73 dBFS at 1.8 GHz A at 2.0 dBFS IN Integer clock with divide by 2 and divide by 4 options 59 dBFS at 5.53 GHz A at 2.0 dBFS IN Flexible JESD204B lane configurations full-scale voltage = 1.1 V p-p On-chip dither SNR at 2.56 GSPS encode 59.7 dBFS at 1.8 GHz A at 2.0 dBFS IN APPLICATIONS 53.0 dBFS at 5.53 GHz A at 2.0 dBFS IN Diversity multiband and multimode digital receivers full-scale voltage = 1.1 V p-p 3G/4G, TD-SCDMA, W-CDMA, and GSM, LTE, LTE-A SFDR at 2.0 GSPS encode Electronic test and measurement systems 78 dBFS at 900 MHz A at 2.0 dBFS IN Phased array radar and electronic warfare 62 dBFS at 5.53 GHz A at 2.0 dBFS IN DOCSIS 3.0 CMTS upstream receive paths full-scale voltage = 1.1 V p-p HFC digital reverse path receivers SNR at 2.0 GSPS encode 62.7 dBFS at 900 MHz A at 2.0 dBFS IN 53.1 dBFS at 5.5 GHz A at 2.0 dBFS IN full-scale voltage = 1.1 V p-p FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 AVDD3 AVDD1 SR DVDD DRVDD1 DRVDD2 SPIVDD (0.975V) (1.9V) (2.5V) (0.975V) (0.975V) (0.975V) (1.9V) (1.9V) BUFFER 14 VIN+A ADC CORE VINA SERDOUT0 DIGITAL DOWN- CONVERTER SERDOUT1 JESD204B SERDOUT2 8 FAST SIGNAL LINK SERDOUT3 DETECT MONITOR AND SERDOUT4 Tx DIGITAL DOWN- OUTPUTS SERDOUT5 CONVERTER SERDOUT6 14 VIN+B SERDOUT7 ADC VINB CORE BUFFER VREF SYNCINB PDWN/STBY JESD204B CLOCK FD A/GPIO A0 SYSREF SUBCLASS 1 DISTRIBUTION CONTROL GPIO A1 GPIO MUX CLK+ FD B/GPIO B0 SPI AND GPIO B1 CONTROL REGISTERS CLK 2 AD9689 4 AGND SDIO SCLK CSB DRGND DGND Figure 1. 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PROGRAMMABLE FIR FILTER CROSSBAR MUX CROSSBAR MUX 15550-001AD9689 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DDC Frequency Translation ..................................................... 47 DDC Decimation Filters ........................................................... 55 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 DDC Gain Stage ......................................................................... 61 Revision History ............................................................................... 3 DDC Complex to Real Conversion ......................................... 61 General Description ......................................................................... 4 DDC Mixed Decimation Settings ............................................ 62 Product Highlights ........................................................................... 4 DDC Example Configurations ................................................. 64 Specif icat ions ..................................................................................... 5 DDC Power Consumption ........................................................ 67 DC Specifications ......................................................................... 5 Signal Monitor ................................................................................ 68 SPORT over JESD204B .............................................................. 69 AC Specifications .......................................................................... 6 Digital Outputs ............................................................................... 71 Digital Specifications ................................................................... 8 Switching Specifications .............................................................. 9 Introduction to the JESD204B Interface ................................. 71 Timing Specifications ................................................................ 10 JESD204B Overview .................................................................. 71 Absolute Maximum Ratings .......................................................... 12 Functional Overview ................................................................. 72 Thermal Resistance .................................................................... 12 JESD204B Link Establishment ................................................. 72 ESD Caution ................................................................................ 12 Physical Layer (Driver) Outputs .............................................. 74 Pin Configuration and Function Descriptions ........................... 13 f 4 Mode .................................................................................. 75 S Typical Performance Characteristics ........................................... 16 Setting Up the AD9689 Digital Interface ................................. 76 2.0 GSPS ....................................................................................... 16 Deterministic Latency .................................................................... 83 2.6 GSPS ....................................................................................... 21 Subclass 0 Operation .................................................................. 83 Equivalent Circuits ......................................................................... 26 Subclass 1 Operation .................................................................. 83 Theory of Operation ...................................................................... 28 Multichip Synchronization ............................................................ 85 ADC Architecture ...................................................................... 28 Normal Mode .............................................................................. 85 Analog Input Considerations .................................................... 28 Timestamp Mode ....................................................................... 85 Voltage Reference ....................................................................... 31 SYSREF Input .............................................................................. 87 DC Offset Calibration ................................................................ 32 SYSREF Setup/Hold Window Monitor ................................. 89 Clock Input Considerations ...................................................... 32 Latency ............................................................................................. 91 Power-Down and Standby Mode ............................................. 35 End to End Total Latency .......................................................... 91 Temperature Diode .................................................................... 35 Example Latency Calculations.................................................. 91 ADC Overrange and Fast Detect .................................................. 37 LMFC Referenced Latency ........................................................ 91 ADC Overrange .......................................................................... 37 Test Modes ....................................................................................... 93 Fast Threshold Detection (FD A and FD B) ........................ 37 ADC Test Modes ........................................................................ 93 ADC Application Modes and JESD204B Tx Converter Mapping JESD204B Block Test Modes .................................................... 94 ........................................................................................................... 38 Serial Port Interface ........................................................................ 96 Programmable FIR Filters ............................................................. 40 Configuration Using the SPI ..................................................... 96 Supported Modes........................................................................ 40 Hardware Interface ..................................................................... 96 Programming Instructions ........................................................ 42 SPI Accessible Features .............................................................. 96 Digital Downconverter (DDC) ..................................................... 44 Memory Map .................................................................................. 97 DDC I/Q Input Selection .......................................................... 44 Reading the Memory Map Register Table ............................... 97 DDC I/Q Output Selection ....................................................... 44 Memory Map Register Details .................................................. 98 DDC General Description ........................................................ 44 Applications Information ............................................................ 132 Rev. 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