a AD9830 FEATURES GENERAL DESCRIPTION +5 V Power Supply This DDS device is a numerically controlled oscillator em- 50 MHz Speed ploying a phase accumulator, a sine look-up table and a On-Chip SINE Look-Up Table 10-bit D/A converter integrated on a single CMOS chip. On-Chip 10-Bit DAC Modulation capabilities are provided for phase modulation Parallel Loading and frequency modulation. Power-Down Option Clock rates up to 50 MHz are supported. Frequency accu- 72 dB SFDR racy can be controlled to one part in 4 billion. Modulation 250 mW Power Consumption is effected by loading registers through the parallel micro- 48-Pin QFP processor interface. APPLICATIONS A power-down pin allows external control of a power-down DDS Tuning mode. The part is available in a 48-pin QFP package. Digital Demodulation FUNCTIONAL BLOCK DIAGRAM DVDD DGND AVDD AGND REFOUT FS ADJUST REFIN MCLK ON-BOARD FULL SCALE REFERENCE COMP CONTROL FSELECT 12 FREQ0 REG IOUT PHASE SIN ACCUMULATOR 10-BIT DAC MUX ROM IOUT (32-BIT) FREQ1 REG PHASE0 REG AD9830 PHASE1 REG MUX PHASE2 REG PHASE3 REG SLEEP PARALLEL REGISTER TRANSFER CONTROL RESET MPU INTERFACE D0 D15 A0 A1 A2 PSEL0 PSEL1 WR REV. B Information furnished by Analog Devices is believed to be accurate and Analog Devices, Inc., reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: (V = +5 V 6 5% AGND = DGND = 0 V T = T to T REFIN = REFOUT 1 DD A MIN MAX AD9830SPECIFICATIONS R = 1 kV R = 51 V for IOUT and IOUT unless otherwise noted) SET LOAD Parameter AD9830A Units Test Conditions/Comments SIGNAL DAC SPECIFICATIONS Resolution 10 Bits Update Rate (f ) 50 MSPS max MAX I Full Scale 20 mA max OUT Output Compliance 1 V max DC Accuracy Integral Nonlinearity 1 LSB typ Differential Nonlinearity 0.5 LSB typ 2 DDS SPECIFICATIONS Dynamic Specifications Signal-to-Noise Ratio 50 dB min f = f , f = 2 MHz MCLK MAX OUT Total Harmonic Distortion 53 dBc max f = f , f = 2 MHz MCLK MAX OUT 3 Spurious Free Dynamic Range (SFDR) f = 6.25 MHz, f = 2.11 MHz MCLK OUT Narrow Band (50 kHz) 72 dBc min (200 kHz) 68 dBc min Wide Band (2 MHz) 50 dBc min Clock Feedthrough 55 dBc typ Wake Up Time 1 ms typ Power-Down Option Yes VOLTAGE REFERENCE Internal Reference +25C 1.21 Volts typ T to T 1.21 7% Volts min/max MIN MAX REFIN Input Impedance 10 M typ Reference TC 100 ppm/C typ REFOUT Impedance 300 typ LOGIC INPUTS V , Input High Voltage V 0.9 V min INH DD V , Input Low Voltage 0.9 V max INL I , Input Current 10 A max INH C , Input Capacitance 10 pF max IN POWER SUPPLIES f = 2 MHz OUT AVDD 4.75/5.25 V min/V max DVDD 4.75/5.25 V min/V max I 25 mA max AA I 6 + 0.5/MHz mA typ DD 4 I + I 60 mA max AA DD 5 Low Power Sleep Mode 0.25 mA typ 1 M Resistor Tied Between 1 mA max REFOUT and AGND NOTES 1 Operating temperature range is as follows: A Version: 40C to +85C. R 10nF SET 2 All dynamic specifications are measured using IOUT. 100% production tested. 1k 3 f = 6.25 MHz, Frequency Word = 5671C71C HEX, f = 2.11 MHz. MCLK OUT 4 Measured with the digital inputs static and equal to 0 V or DVDD. REFOUT REFIN FS AVDD 5 The Low Power Sleep Mode current is 2 mA typically when a 1 M resistor is ADJUST not tied from REFOUT to AGND. ON-BOARD 10nF REFERENCE COMP FULL-SCALE The AD9830 is tested with a capacitive load of 50 pF. The part can be operated CONTROL with higher capacitive loads, but the magnitude of the analog output will be attenu- ated. For example, a 10 MHz output signal will be attenuated by 3 dB when the IOUT load capacitance equals 250 pF. 12 SIN 10-BIT ROM DAC 51 Specifications subject to change without notice. 50pF IOUT 51 50pF Figure 1. Test Circuit with Which Specifications Are Tested 2 REV. B