20 mW Power, 2.3 V to 5.5 V, 75 MHz Complete DDS Data Sheet AD9834 Capability for phase modulation and frequency modulation is FEATURES provided. The frequency registers are 28 bits with a 75 MHz clock Narrow-band SFDR >72 dB rate, resolution of 0.28 Hz can be achieved. Similarly, with a 1 MHz 2.3 V to 5.5 V power supply clock rate, the AD9834 can be tuned to 0.004 Hz resolution. Output frequency up to 37.5 MHz Frequency and phase modulation are affected by loading registers Sine output/triangular output through the serial interface and toggling the registers using On-board comparator software or the FSELECT pin and PSELECT pin, respectively. 3-wire SPI interface Extended temperature range: 40C to +105C The AD9834 is written to using a 3-wire serial interface. This Power-down option serial interface operates at clock rates up to 40 MHz and is 20 mW power consumption at 3 V compatible with DSP and microcontroller standards. 20-lead TSSOP The device operates with a power supply from 2.3 V to 5.5 V. APPLICATIONS The analog and digital sections are independent and can be run Frequency stimulus/waveform generation from different power supplies, for example, AVDD can equal Frequency phase tuning and modulation 5 V with DVDD equal to 3 V. Low power RF/communications systems The AD9834 has a power-down pin (SLEEP) that allows Liquid and gas flow measurement external control of the power-down mode. Sections of the Sensory applications: proximity, motion, and defect device that are not being used can be powered down to detection minimize the current consumption. For example, the DAC can Test and medical equipment be powered down when a clock output is being generated. GENERAL DESCRIPTION The part is available in a 20-lead TSSOP. The AD9834 is a 75 MHz low power DDS device capable of producing high performance sine and triangular outputs. It also has an on-board comparator that allows a square wave to be produced for clock generation. Consuming only 20 mW of power at 3 V makes the AD9834 an ideal candidate for power-sensitive applications. FUNCTIONAL BLOCK DIAGRAM AVDD AGND DGND DVDD CAP/2.5V REFOUT FS ADJUST REGULATOR ON-BOARD REFERENCE MCLK VCC FULL-SCALE 2.5V COMP CONTROL FSELECT 28-BIT FREQ0 REG PHASE 12 IOUT SIN 10-BIT ACCUMULATOR MUX MUX ROM DAC (28-BIT) IOUTB 28-BIT FREQ1 REG MSB 12-BIT PHASE0 REG MUX MUX 12-BIT PHASE1 REG DIVIDED BY 2 16-BIT CONTROL MUX SIGN BIT OUT REGISTER SERIAL INTERFACE COMPARATOR VIN AND CONTROL LOGIC AD9834 FSYNC SCLK SDATA PSELECT SLEEP RESET Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20032014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 02705-001AD9834* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS DOCUMENTATION View a parametric search of comparable parts. Application Notes AN-1044: Programming the AD5932 for Frequency Sweep and Single Frequency Outputs EVALUATION KITS AN-1070: Programming the AD9833/AD9834 AD9834 Evaluation Board AN-1248: SPI Interface AN-1389: Recommended Rework Procedure for the Lead Frame Chip Scale Package (LFCSP) AN-237: Choosing DACs for Direct Digital Synthesis AN-280: Mixed Signal Circuit Technologies AN-342: Analog Signal-Handling for High Speed and Accuracy AN-345: Grounding for Low-and-High-Frequency Circuits AN-419: A Discrete, Low Phase Noise, 125 MHz Crystal Oscillator for the AD9850 AN-423: Amplitude Modulation of the AD9850 Direct Digital Synthesizer AN-543: High Quality, All-Digital RF Frequency Modulation Generation with the ADSP-2181 and the AD9850 DDS AN-557: An Experimenter s Project: AN-587: Synchronizing Multiple AD9850/AD9851 DDS- Based Synthesizers AN-605: Synchronizing Multiple AD9852 DDS-Based Synthesizers AN-621: Programming the AD9832/AD9835 AN-632: Provisionary Data Rates Using the AD9951 DDS as an Agile Reference Clock for the ADN2812 Continuous- Rate CDR AN-769: Generating Multiple Clock Outputs from the AD9540 AN-772: A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP) AN-823: Direct Digital Synthesizers in Clocking Applications Time AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance AN-843: Measuring a Loudspeaker Impedance Profile Using the AD5933 AN-847: Measuring a Grounded Impedance Profile Using the AD5933 AN-851: A WiMax Double Downconversion IF Sampling Receiver Design