CMOS, 125 MHz a Complete DDS Synthesizer AD9850 FEATURES FUNCTIONAL BLOCK DIAGRAM 125 MHz Clock Rate +V GND S On-Chip High Performance DAC and High Speed DAC R Comparator SET REF HIGH SPEED DAC SFDR > 50 dB 40 MHz A CLOCK IN 10-BIT OUT ANALOG DDS DAC OUT MASTER 32-Bit Frequency Tuning Word RESET PHASE Simplified Control Interface: Parallel Byte or Serial 32-BIT AND TUNING Loading Format CONTROL ANALOG WORD WORDS IN Phase Modulation Capability FREQUENCY UPDATE/ FREQUENCY/PHASE 3.3 V or 5 V Single-Supply Operation DATA REGISTER DATA REGISTER CLOCK OUT RESET Low Power: 380 mW 125 MHz (5 V) CLOCK OUT WORD LOAD Low Power: 155 mW 110 MHz (3.3 V) COMPARATOR DATA INPUT REGISTER CLOCK Power-Down Function SERIAL PARALLEL AD9850 Ultrasmall 28-Lead SSOP Packaging LOAD LOAD 1-BIT 8-BITS APPLICATIONS 40 LOADS 5 LOADS Frequency/PhaseAgile Sine Wave Synthesis FREQUENCY, PHASE, AND CONTROL DATA INPUT Clock Recovery and Locking Circuitry for Digital Communications Digitally Controlled ADC Encode Generator Agile Local Oscillator Applications GENERAL DESCRIPTION 11.25, and any combination thereof. The AD9850 also contains The AD9850 is a highly integrated device that uses advanced a high speed comparator that can be configured to accept the DDS technology coupled with an internal high speed, high (externally) filtered output of the DAC to generate a low jitter performance D/A converter and comparator to form a com- square wave output. This facilitates the devices use as an plete, digitally programmable frequency synthesizer and agile clock generator function. clock generator function. When referenced to an accurate The frequency tuning, control, and phase modulation words are clock source, the AD9850 generates a spectrally pure, fre- loaded into the AD9850 via a parallel byte or serial loading quency/phase programmable, analog output sine wave. This format. The parallel load format consists of five iterative loads sine wave can be used directly as a frequency source, or it can of an 8-bit control word (byte). The first byte controls phase be converted to a square wave for agile-clock generator applica- modulation, power-down enable, and loading format Bytes 2 to tions. The AD9850s innovative high speed DDS core provides 5 comprise the 32-bit frequency tuning word. Serial loading is a 32-bit frequency tuning word, which results in an output accomplished via a 40-bit serial data stream on a single pin. The tuning resolution of 0.0291 Hz for a 125 MHz reference clock AD9850 Complete DDS uses advanced CMOS technology to input. The AD9850s circuit architecture allows the generation provide this breakthrough level of functionality and performance of output frequencies of up to one-half the reference clock on just 155 mW of power dissipation (3.3 V supply). frequency (or 62.5 MHz), and the output frequency can be digi- The AD9850 is available in a space-saving 28-lead SSOP, tally changed (asynchronously) at a rate of up to 23 million new surface-mount package. It is specified to operate over the frequencies per second. The device also provides five bits of extended industrial temperature range of 40C to +85C. digitally controlled phase modulation, which enables phase shifting of its output in increments of 180, 90, 45, 22.5, REV. H Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/326-8703 2004 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective owners.AD9850SPECIFICATIONS (V = 5 V 5% except as noted, R = 3.9 k ) S SET AD9850BRS Parameter Temp Test Level Min Typ Max Unit CLOCK INPUT CHARACTERISTICS Frequency Range 5 V Supply Full IV 1 125 MHz 3.3 V Supply Full IV 1 110 MHz Pulse Width High/Low 5 V Supply 25CIV 3.2 ns 3.3 V Supply 25CIV 4.1 ns DAC OUTPUT CHARACTERISTICS Full-Scale Output Current R = 3.9 k 25CV 10.24 mA SET R = 1.95 k 25CV 20.48 mA SET Gain Error 25CI 10 +10 % FS Gain Temperature Coefficient Full V 150 ppm/C Output Offset 25CI 10 A Output Offset Temperature Coefficient Full V 50 nA/C Differential Nonlinearity 25CI 0.5 0.75 LSB Integral Nonlinearity 25CI 0.5 1 LSB Output Slew Rate (50 , 2 pF Load) 25CV 400 V/s Output Impedance 25CIV 50 120 k Output Capacitance 25CIV 8 pF Voltage Compliance 25CI 1.5 V Spurious-Free Dynamic Range (SFDR) Wideband (Nyquist Bandwidth) 1 MHz Analog Out 25CIV 63 72 dBc 20 MHz Analog Out 25CIV 50 58 dBc 40 MHz Analog Out 25CIV 46 54 dBc Narrowband 40.13579 MHz 50 kHz 25CIV 80 dBc 40.13579 MHz 200 kHz 25CIV 77 dBc 4.513579 MHz 50 kHz/20.5 MHz CLK 25CIV 84 dBc 4.513579 MHz 200 kHz/20.5 MHz CLK 25CIV 84 dBc COMPARATOR INPUT CHARACTERISTICS Input Capacitance 25CV 3 pF Input Resistance 25CIV 500 k Input Current 25CI 12 +12 A Input Voltage Range 25CIV 0 V V DD Comparator Offset* Full VI 30 30 mV COMPARATOR OUTPUT CHARACTERISTICS Logic 1 Voltage 5 V Supply Full VI 4.8 V Logic 1 Voltage 3.3 V Supply Full VI 3.1 V Logic 0 Voltage Full VI 0.4 V Propagation Delay, 5 V Supply (15 pF Load) 25CV 5.5 ns Propagation Delay, 3.3 V Supply (15 pF Load) 25CV 7 ns Rise/Fall Time, 5 V Supply (15 pF Load) 25CV 3 ns Rise/Fall Time, 3.3 V Supply (15 pF Load) 25CV 3.5 ns Output Jitter (p-p) 25CV 80 ps CLOCK OUTPUT CHARACTERISTICS Clock Output Duty Cycle (Clk Gen. Config.) 25CIV 50 10 % 2 REV. H