MUX MUX CMOS 300 MSPS Complete DDS Data Sheet AD9852 FEATURES Frequency ramped FSK <25 ps rms total jitter in clock generator mode 300 MHz internal clock rate Automatic bidirectional frequency sweeping FSK, BPSK, PSK, chirp, AM operation Sin(x)/x correction Dual integrated 12-bit D/A converters Simplified control interface Ultrahigh speed comparator, 3 ps rms jitter 10 MHz serial 2-wire or 3-wire SPI-compatible Excellent dynamic performance 100 MHz parallel 8-bit programming 80 dB SFDR at 100 MHz (1 MHz) A OUT 3.3 V single supply 4 to 20 programmable reference clock multiplier Multiple power-down functions Dual 48-bit programmable frequency registers Single-ended or differential input reference clock Dual 14-bit programmable phase offset registers Small, 80-lead LQFP or TQFP with exposed pad 12-bit programmable amplitude modulation and on/off output shaped keying function APPLICATIONS Single-pin FSK and BPSK data interfaces Agile LO frequency synthesis PSK capability via I/O interface Programmable clock generator Linear or nonlinear FM chirp functions with single pin FM chirp source for radar and scanning systems frequency hold function Test and measurement equipment Commercial and amateur RF exciter FUNCTIONAL BLOCK DIAGRAM DIGITAL MULTIPLIERS SYSTEM CLOCK INV DDS CORE 12 SINC 12 4 TO 20 12-BIT ANALOG REFERENCE I FILTER REFCLK REFCLK COSINE OUT CLOCK IN BUFFER MULTIPLIER DAC 48 48 17 16 SYSTEM DAC R SET CLOCK DIFF/SINGLE MUX SELECT 12-BIT ANALOG SYSTEM CONTROL CLOCK 14 OUT 48 DAC Q 12 3 FSK/BPSK/HOLD MUX MUX MUX ANALOG DATA IN IN DELTA PROGRAMMABLE FREQUENCY SYSTEM AMPLITUDE AND RATE TIMER CLOCK RATE CONTROL 2 48 48 48 14 COMPARATOR SYSTEM 14 12 CLOCK CLOCK SECOND 14-BIT AM 12-BIT DC DELTA FREQUENCY FREQUENCY FIRST 14-BIT OUT FREQUENCY TUNING TUNING PHASE/OFFSET PHASE/OFFSET MODULATION CONTROL WORD WORD 1 WORD 2 WORD WORD MODE SELECT PROGRAMMING REGISTERS OSK SYSTEM SYSTEM CLK AD9852 CLOCK 2 BUS CLOCK Q GND D BIDIRECTIONAL INT INTERNAL I/O PORT BUFFERS INTERNAL/EXTERNAL PROGRAMMABLE +V S I/O UPDATE CLOCK UPDATE CLOCK EXT READ WRITE SERIAL/ 6-BIT ADDRESS 8-BIT MASTER PARALLEL OR SERIAL PARALLEL RESET SELECT PROGRAMMING LOAD LINES Figure 1. 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DEMUX FREQUENCY ACCUMULATOR ACC 1 PHASE ACCUMULATOR ACC 2 PHASE-TO- AMPLITUDE CONVERTER 0063 4-0 01AD9852 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Cosine DAC ................................................................................ 29 Applications ....................................................................................... 1 Control DAC ............................................................................... 29 Functional Block Diagram .............................................................. 1 Inverse Sinc Function ................................................................ 29 Revision History ............................................................................... 2 REFCLK Multiplier .................................................................... 29 General Description ......................................................................... 4 High Speed Comparator ............................................................ 30 O ver vie w ........................................................................................ 4 Power-Down ............................................................................... 30 Specif icat ions ..................................................................................... 5 Programming the AD9852 ............................................................ 31 Absolute Maximum Ratings ............................................................ 8 MASTER RESET ........................................................................ 31 Thermal Resistance ...................................................................... 8 Parallel I/O Operation ............................................................... 31 Explanation of Test Levels ........................................................... 8 Serial Port I/O Operation .......................................................... 31 ESD Caution .................................................................................. 8 General Operation of the Serial Interface ................................... 34 Pin Configuration and Function Descriptions ............................. 9 Instruction Byte .......................................................................... 34 Typical Performance Characteristics ........................................... 12 Serial Interface Port Pin Descriptions ..................................... 35 Typical Applications ....................................................................... 16 MSB/LSB Transfers .................................................................... 35 Modes of Operation ....................................................................... 18 Control Register Descriptions .................................................. 36 Single Tone (Mode 000) ............................................................. 18 Power Dissipation and Thermal Considerations ....................... 38 Unramped FSK (Mode 001) ...................................................... 19 Thermal Impedance ................................................................... 38 Ramped FSK (Mode 010) .......................................................... 19 Junction Temperature Considerations .................................... 38 Chirp (Mode 011) ....................................................................... 22 Evaluation of Operating Conditions ............................................ 40 BPSK (Mode 100) ....................................................................... 26 Thermally Enhanced Package Mounting Guidelines ............ 40 Using the AD9852 .......................................................................... 27 Outline Dimensions ....................................................................... 41 Internal and External Update Clock ........................................ 27 Ordering Guide .......................................................................... 41 On/Off Output Shaped Keying (OSK) .................................... 27 REVISION HISTORY 5/2007Rev. D to Rev. E 8/2019Rev. E to Rev. F Changed AD9852ASQ to AD9852ASVZ ........................ Universal Changes to Figure 1 .......................................................................... 1 Changed AD9852AST to AD9852ASTZ ......................... Universal Changes to General Description Section ...................................... 4 Change to Features ............................................................................ 1 Deleted Evaluation Board Section ................................................ 41 Changes to Endnote 10 of Table 1 ................................................... 7 Deleted Table 14, Renumbered Sequentially .............................. 41 Changes to Absolute Maximum Ratings ........................................ 8 Changes to Ordering Guide .......................................................... 41 Added Thermal Resistance Section ................................................ 8 Deleted Table 15 .............................................................................. 44 Change to Ramped FSK (Mode 010) Section ............................. 19 Deleted Figure 61, Renumbered Sequentially ............................ 46 Change to Internal and External Update Clock Section ........... 27 Deleted Figure 62 ............................................................................ 47 Change to Thermal Impedance Section ...................................... 38 Deleted Figure 63 and Figure 64 ................................................... 48 Changes to Junction Temperature Considerations Section ...... 38 Deleted Figure 65 and Figure 66 ................................................... 49 Changes to Thermally Enhanced Package Mounting Deleted Figure 67 ............................................................................ 50 Guidelines Section .......................................................................... 40 Deleted Figure 61 to Figure 64...................................................... 41 Rev. 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