CMOS 200 MHz Quadrature Digital Upconverter AD9856 APPLICATIONS FEATURES HFC data, telephony, and video modems Universal low cost modulator solution for communications applications Wireless and satellite communications DC to 80 MHz output bandwidth Cellular base stations Integrated 12-bit D/A converter Programmable sample rate interpolation filter GENERAL DESCRIPTION Programmable reference clock multiplier The AD9856 integrates a high speed, direct digital synthesizer Internal SIN(x)/x compensation filter (DDS), a high performance, high speed, 12-bit digital-to-analog >52 dB SFDR 40 MHz AOUT converter (DAC), clock multiplier circuitry, digital filters, and >48 dB SFDR 70 MHz A OUT other DSP functions on a single chip to form a complete >80 dB narrow-band SFDR 70 MHz AOUT quadrature digital upconverter device. The AD9856 is intended +3 V single-supply operation to function as a universal I/Q modulator and agile upconverter Space-saving surface-mount packaging for communications applications where cost, size, power Bidirectional control bus interface dissipation, and dynamic performance are critical attributes. Supports burst and continuous Tx modes Single-tone mode for frequency synthesis applications The AD9856 is available in a space-saving surface-mount Four programmable, pin-selectable, modulator profiles package, and is specified to operate over the extended industrial Direct interface to AD8320/AD8321 PGA cable driver temperature range of 40C to +85C. FUNCTIONAL BLOCK DIAGRAM AD9856 4 TO 8 12 12 2 TO 63 12 12 SELECTABLE SELECTABLE INTERPOLATING INTERPOLATOR HALFBANDS 12 12 INV DC-80 MHz 12-BIT COMPLEX SINC OUTPUT DAC DATA IN 4 TO 8 12 12 2 TO 63 12 12 SELECTABLE DAC SELECTABLE INTERPOLATING R SET INTERPOLATOR HALFBANDS 12 12 SINE COSINE SPI INTERFACE 4 TO 20 PROG. TO AD8320/AD8321 TxENABLE CLOCK DDS AND CONTROL FUNCTIONS PROGRAMMABLE (I/Q SYNC) MULTIPLIER CABLE DRIVER AMPLIFIER REFERENCE PROFILE PROFILE MASTER BIDIRECTIONAL SPI CONTROL INTERFACE: CLOCK IN SELECT SELECT RESET 32-BIT FREQUENCY TUNING WORD 12 34 FREQUENCY UPDATE INTERPOLATION FILTER RATE REFERENCE CLOCK MULTIPLIER RATE SPECTRAL PHASE INVERSION ENABLE CABLE DRIVER AMPLIFIER CONTROL Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 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DEMULTIPLEXER AND SERIAL-TO-PARALLEL CONVERTER 00637-C-001AD9856 TABLE OF CONTENTS Specifications..................................................................................... 3 Digital Quadrature Modulator ................................................. 23 Absolute Maximum Ratings............................................................ 5 Inverse Sinc Filter (ISF) ............................................................. 24 Explanation of Test Levels........................................................... 5 Direct Digital Synthesizer Function ........................................ 25 ESD Caution.................................................................................. 5 D/A Converter............................................................................ 25 Pin Configuration and Function Descriptions............................. 6 Reference Clock Multiplier ....................................................... 26 Typical Performance Characteristics ............................................. 8 Throughput and Latency........................................................... 26 Typical Modulated Output Spectral Plots ................................. 8 Control Interface ........................................................................ 26 Typical Single-Tone Output Spectral Plots ............................... 9 General Operation of the Serial Interface............................... 26 Typical Narrow-Band SFDR Spectral Plots ............................ 10 Instruction Byte.......................................................................... 27 Typical Phase Noise Spectral Plots........................................... 10 Serial Interface Port Pin Descriptions ..................................... 28 Typical Plots of Output Constellations.................................... 11 MSB/LSB Transfers .................................................................... 28 Power Consumption .................................................................. 12 Notes on Serial Port Operation ................................................ 28 Serial Control Bus Register ........................................................... 13 Programming/Writing the AD8320/AD8321 Cable Driver Amplifier Gain Control............................................................. 30 Register Bit Definitions.............................................................. 14 Understanding and Using Pin-Selectable Modulator Profiles Theory of Operation ...................................................................... 15 ....................................................................................................... 31 Modulation Mode Operation ................................................... 15 Power Dissipation Considerations........................................... 31 Input Word Rate (fW) vs. REFCLK Relationship .................... 16 AD9856 Evaluation Board ........................................................ 32 I/Q Data Synchronization ......................................................... 16 Support ........................................................................................ 32 Half-Band Filters (HBFs) .......................................................... 20 Outline Dimensions ....................................................................... 35 Cascaded Integrator Comb (CIC) Filter.................................. 21 Ordering Guide .......................................................................... 35 REVISION HISTORY 1/05Rev. B to Rev. C Updated Format..................................................................Universal Changes to Table 2............................................................................ 5 Changes to Input Word Rate (f ) vs. REFCLK w Relationship Section.................................................................. 16 Changes to Cascaded Integrator Comb (CIC) Filter Section ... 21 Updates to Direct Digital Synthesizer Function Section........... 25 Added Support Section.................................................................. 32 Updated Outline Dimensions ....................................................... 35 Changes to Ordering Guide .......................................................... 35 9/99Rev. A to Rev. B Rev. C Page 2 of 36