CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter AD9857 FEATURES 200 MHz internal clock rate 3.3 V single supply 14-bit data path Single-ended or differential input reference clock Excellent dynamic performance: 80-lead LQFP surface-mount packaging 80 dB SFDR 65 MHz (100 kHz) AOUT Three modes of operation: 4 to 20 programmable reference clock multiplier Quadrature modulator mode Reference clock multiplier PLL lock detect indicator Single-tone mode Internal 32-bit quadrature DDS Interpolating DAC mode FSK capability APPLICATIONS 8-bit output amplitude control HFC data, telephony, and video modems Single-pin power-down function Wireless base station Four programmable, pin-selectable signal profiles Agile, LO frequency synthesis SIN(x)/x correction (inverse SINC function) Broadband communications Simplified control interface 10 MHz serial, 2-wire or 3-wire SPI-compatible FUNCTIONAL BLOCK DIAGRAM INVERSE FIXED AD9857 CIC FILTER QUADRATURE INTER- DAC RSET I PROGRAMMABLE MODULATOR POLATOR INTERPOLATOR 14 14 PARALLEL IOUT CIC 14-BIT INV DATA IN (4 ) 14 - 63 ) DAC (2 INVERSE IOUT CIC (14-BIT) SINC FILTER 8 Q OUTPUT DDS SCALE CORE VALUE TUNING 32 WORD TIMING AND CONTROL CONTROL REGISTERS POWER- PROFILE DOWN SELECT REFCLK CLOCK LOGIC LOGIC MODE MULTIPLIER CONTROL (4 20 ) REFCLK PDCLK/ TxENABLE RESET CIC SERIAL DIGITAL PS1 PS0 PLL CLOCK FUD OVERFLOW PORT POWER- LOCK INPUT DOWN MODE Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 2004 Analog Devices, Inc. All rights reserved. DATA CLOCK DEMUX INVERSE CIC CLOCK INVERSE CIC CONTROL MUX HALF-BAND CLOCKS INTERP CONTROL INTERP CLOCK MUX SIN COS SYNCH CLOCK MUX SYSCLK MUX INVERSE SINC CLOCK MUX DAC CLOCK 01018-C-001AD9857 TABLE OF CONTENTS Input Data Programming .............................................................. 24 Revision History ............................................................................... 3 Control InterfaceSerial I/O ................................................... 24 General Description ......................................................................... 4 General Operation of the Serial Interface............................... 24 Specifications..................................................................................... 5 Instruction Byte.......................................................................... 26 Absolute Maximum Ratings............................................................ 8 Serial Interface Port Pin Descriptions ..................................... 26 Explanation of Test Levels........................................................... 8 Control Register Descriptions .................................................. 27 ESD Caution.................................................................................. 8 Profile 0...................................................................................... 27 Pin Configuration and Function Descriptions............................. 9 Profile 1...................................................................................... 28 Typical Performance Characteristics ........................................... 11 Profile 2...................................................................................... 28 Modulated Output Spectral Plots............................................. 11 Profile 3...................................................................................... 28 Single-Tone Output Spectral Plots ........................................... 12 Latency......................................................................................... 30 Narrow-band SFDR Spectral Plots........................................... 13 Ease of Use Features....................................................................... 32 Output Constellations................................................................ 14 Profile Select................................................................................ 32 Modes Of Operation ...................................................................... 15 Setting the Phase of the DDS.................................................... 32 Quadrature Modulation Mode ................................................. 15 Reference Clock Multiplier ....................................................... 32 Single-Tone Mode ...................................................................... 16 PLL Lock...................................................................................... 32 Interpolating DAC Mode .......................................................... 17 Single or Differential Clock ...................................................... 33 Signal Processing Path ................................................................... 18 CIC Overflow Pin....................................................................... 33 Input Data Assembler ................................................................ 18 Clearing the CIC Filter .............................................................. 33 Inverse CIC Filter ....................................................................... 19 Digital Power-Down .................................................................. 33 Programmable (2 to 63) CIC Interpolating Filter............. 21 Hardware-Controlled Digital Power-Down ........................... 34 Quadrature Modulator .............................................................. 21 Software-Controlled Digital Power-Down ............................. 34 DDS Core..................................................................................... 21 Full Sleep Mode .......................................................................... 34 Inverse SINC Filter..................................................................... 22 Power Management Considerations........................................ 34 Output Scale Multiplier ............................................................. 22 Support ........................................................................................ 35 14-Bit D/A Converter ................................................................ 22 Outline Dimensions ....................................................................... 38 Reference Clock Multiplier ....................................................... 23 Ordering Guide .......................................................................... 39 Rev. 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