100 MSPS/140 MSPS
a
Analog Flat Panel Interface
AD9884A
FEATURES FUNCTIONAL BLOCK DIAGRAM
140 MSPS Maximum Conversion Rate
500 MHz Analog Bandwidth
AD9884A
0.5 V to 1.0 V Analog Input Range 8
R
OUTA
8
400 ps p-p PLL Clock Jitter
R
IN CLAMP A/D
8
Power-Down Mode
R
OUTB
3.3 V Power Supply
8
2.5 V to 3.3 V Three-State CMOS Outputs G
OUTA
88
G
IN A/D
Demultiplexed Output Ports CLAMP
8
G
OUTB
Data Clock Output Provided
Low Power: 570 mW Typical
8
B
OUTA
Internal PLL Generates CLOCK from HSYNC
88
B CLAMP A/D
IN
8
Serial Port Interface
B
OUTB
Fully Programmable
2
HSYNC
DATACK
Supports Alternate Pixel Sampling for Higher-
COAST
CLOCK HSOUT
Resolution Applications
CLAMP
GENERATOR
CKINV
0.15V
APPLICATIONS
CKEXT CONTROL REF REFIN
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
A A
FILT SOGIN SOGOUT SDA SCL PWRDN REFOUT
0 1
Scan Converters
GENERAL DESCRIPTION 20 MHz to 140 MHz. PLL clock jitter is typically 400 ps p-p
The AD9884A is a complete 8-bit 140 MSPS monolithic analog relative to the input reference. When the COAST signal is pre-
interface optimized for capturing RGB graphics signals from sented, the PLL maintains its output frequency in the absence
personal computers and workstations. Its 140 MSPS encode of HSYNC. A 32-step sampling phase adjustment is provided.
rate capability and full-power analog bandwidth of 500 MHz Data, HSYNC and Data Clock output phase relationships are
supports display resolutions of up to 1280 1024 (SXGA) at always maintained. The PLL can be disabled and an external
75 Hz with sufficient input bandwidth to accurately acquire and clock input provided as the pixel clock.
digitize each pixel.
A clamp signal is generated internally or may be provided by the
To minimize system cost and power dissipation, the AD9884A user through the CLAMP input pin. This device is fully program-
includes an internal 1.25 V reference, PLL to generate a pixel mable via a two-wire serial port.
clock from HSYNC, and programmable gain, offset and clamp
Fabricated in an advanced CMOS process, the AD9884A is
circuits. The user provides only a 3.3 V power supply, analog
provided in a space-saving 128-lead MQFP surface mount plastic
input, and HSYNC signals. Three-state CMOS outputs may be
package and is specified over a 0C to +70C temperature range.
powered by a supply between 2.5 V and 3.3 V.
The AD9884As on-chip PLL generates a pixel clock from the
HSYNC input. Pixel clock output frequencies range from
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com
under any patent or patent rights of Analog Devices.
Fax: 781/326-8703 Analog Devices, Inc., 2001(V = 3.3 V, V = 3.3 V, PV = 3.3 V, ADC Clock Frequency = Maximum, PLL
D DD D
Clock Frequency = Maximum, Control Registers Programmed to Default State)
AD9884ASPECIFICATIONS
Test AD9884AKS-100 AD9884AKS-140
Parameter Temp Level Min Typ Max Min Typ Max Unit
RESOLUTION 8 8 Bits
DC ACCURACY
Differential Nonlinearity 25CI 0.5 1.0 0.5 +1.15/1.0 LSB
Full VI 1.0 +1.25/1.0 LSB
Integral Nonlinearity 25CI 0.5 1.25 0.8 1.4 LSB
Full VI 1.75 2.5 LSB
No Missing Codes Full VI Guaranteed Guaranteed
ANALOG INPUT
Input Voltage Range
Minimum Full VI 0.5 0.5 V p-p
Maximum Full VI 1.0 1.0 V p-p
Gain Tempco 25C V 100 280 ppm/C
Input Bias Current 25CI 1 1 A
Full VI 1 1 A
Input Offset Voltage Full VI 7 50 7 50 mV
Input Full-Scale Matching Full VI 1.5 5.0 1.5 5.0 %FS
Offset Adjustment Range Full VI 22 23.5 25 22 23.5 25 %FS
REFERENCE OUTPUT
Output Voltage Full VI 1.20 1.25 1.30 1.20 1.25 1.30 V
Temperature Coefficient Full V 50 50 ppm/C
SWITCHING PERFORMANCE
Maximum Conversion Rate Full VI 100 140 MSPS
Minimum Conversion Rate Full IV 10 10 MSPS
Data to Clock Skew, t Full IV 0.5 +2.0 0.5 +2.0 ns
SKEW
t Full VI 4.7 4.7 s
BUFF
t Full VI 4.0 4.0 s
STAH
t Full VI 0 0 s
DHO
t Full VI 4.7 4.7 s
DAL
t Full VI 4.0 4.0 s
DAH
t Full VI 250 250 ns
DSU
t Full VI 4.7 4.7 s
STASU
t Full VI 4.0 4.0 s
STOSU
HSYNC Input Frequency Full IV 15 110 15 110 kHz
Maximum PLL Clock Rate Full VI 100 140 MHz
Minimum PLL Clock Rate Full IV 20 20 MHz
1 2
PLL Jitter 25C IV 400 700 475 750 ps p-p
1 2
Full IV 1000 1000 ps p-p
Sampling Phase Tempco Full IV 15 15 ps/C
DIGITAL INPUTS
Input Voltage, High (V ) Full VI 2.5 2.5 V
IH
Input Voltage, Low (V ) Full VI 0.8 0.8 V
IL
Input Current, High (I ) Full VI 1.0 1.0 A
IH
Input Current, Low (I ) Full VI +1.0 +1.0 A
IL
Input Capacitance 25CV 3 3 pF
DIGITAL OUTPUTS
Output Voltage, High (V ) Full VI V 0.1 V 0.1 V
OH DD DD
Output Voltage, Low (V ) Full VI 0.1 0.1 V
OL
Duty Cycle
DATACK, DATACK Full IV 45 50 55 45 50 55 %
Output Coding Binary Binary
2 REV. C