AD9910BSVZ-REEL Analog Devices

1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer Data Sheet AD9910 FEATURES APPLICATIONS 1 GSPS internal clock speed (up to 400 MHz analog output) Agile local oscillator (LO) frequency synthesis Integrated 1 GSPS, 14-bit DAC Programmable clock generators 0.23 Hz or better frequency resolution FM chirp source for radar and scanning systems Phase noise 125 dBc/Hz 1 kHz offset (400 MHz carrier) Test and measurement equipment Excellent dynamic performance with Acousto-optic device drivers >80 dB narrow-band SFDR Polar modulators Serial input/output (I/O) control Fast frequency hopping Automatic linear or arbitrary frequency, phase, and amplitude sweep capability 8 frequency and phase offset profiles Sin(x)/(x) correction (inverse sinc filter) 1.8 V and 3.3 V power supplies Software and hardware controlled power-down 100-lead TQFP EP package Integrated 1024 word 32-bit RAM PLL REFCLK multiplier Parallel datapath interface Internal oscillator can be driven by a single crystal Phase modulation capability Amplitude modulation capability Multichip synchronization FUNCTIONAL BLOCK DIAGRAM AD9910 HIGH SPEED PARALLEL DATA INTERFACE LINEAR RAMP GENERATOR 1GSPS DDS CORE 14-BIT DAC 1024- ELEMENT RAM REFCLK TIMING AND CONTROL MULTIPLIER SERIAL CONTROL DATA PORT Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20072016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 06479-001AD9910 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Output Shift Keying (OSK) ....................................................... 26 Applications ....................................................................................... 1 Digital Ramp Generator (DRG) ............................................... 27 Functional Block Diagram .............................................................. 1 RAM Control .............................................................................. 32 Revision History ............................................................................... 3 Additional Features ........................................................................ 41 General Description ......................................................................... 4 Profiles ......................................................................................... 41 Specifications ..................................................................................... 5 I/O UPDATE, SYNC CLK, and System Clock Relationships ....................................................................................................... 41 Electrical Specifications ............................................................... 5 Automatic I/O Update ............................................................... 42 Absolute Maximum Ratings ............................................................ 8 Power-Down Control ................................................................ 42 Equivalent Circuits ....................................................................... 8 Synchronization of Multiple Devices ........................................... 43 ESD Caution .................................................................................. 8 Power Supply Partitioning ............................................................. 46 Pin Configuration and Function Descriptions ............................. 9 3.3 V Supplies .............................................................................. 46 Typical Performance Characteristics ........................................... 12 1.8 V Supplies .............................................................................. 46 Application Circuits ....................................................................... 15 Serial Programming ....................................................................... 47 Theory of Operation ...................................................................... 16 Control InterfaceSerial I/O ................................................... 47 Single Tone Mode ....................................................................... 16 General Serial I/O Operation ................................................... 47 RAM Modulation Mode ............................................................ 17 Instruction Byte .......................................................................... 47 Digital Ramp Modulation Mode .............................................. 18 Serial I/O Port Pin Descriptions .............................................. 47 Parallel Data Port Modulation Mode ....................................... 19 Serial I/O Timing Diagrams ..................................................... 48 Mode Priority .............................................................................. 21 MSB/LSB Transfers .................................................................... 48 Functional Block Detail ................................................................. 22 Register Map and Bit Descriptions .............................................. 49 DDS Core ..................................................................................... 22 Register Bit Descriptions ........................................................... 54 14-Bit DAC Output .................................................................... 22 Outline Dimensions ....................................................................... 61 Inverse Sinc Filter ....................................................................... 23 Ordering Guide .......................................................................... 61 Clock Input (REF CLK/REF CLK) ........................................ 23 PLL Lock Indication ................................................................... 26 Rev. E Page 2 of 64