400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer Data Sheet AD9954 FEATURES GENERAL DESCRIPTION 400 MSPS internal clock speed The AD9954 is a direct digital synthesizer (DDS) that uses Integrated 14-bit DAC advanced technology, coupled with an internal high speed, high Programmable phase/amplitude dithering performance DAC to form a complete, digitally programmable, 32-bit frequency tuning accuracy high frequency synthesizer capable of generating a frequency- 14-bit phase tuning accuracy agile analog output sinusoidal waveform at up to 160 MHz. Phase noise better than 120 dBc/Hz The AD9954 enables fast frequency hopping coupled with fine Excellent dynamic performance tuning of both frequency (0.01 Hz or better) and phase (0.022 >80 dB narrowband SFDR granularity). Serial input/output (I/O) control The AD9954 is programmed via a high speed serial I/O port. Ultrahigh speed analog comparator The device includes static RAM to support flexible frequency Automatic linear and nonlinear frequency sweeping sweep capability in several modes, plus a user-defined linear 4 frequency/phase offset profiles sweep mode of operation. Also included is an on-chip high 1.8 V power supply speed comparator for applications requiring a square wave Software and hardware controlled power-down output. An on-chip oscillator and PLL circuitry provide users 48-lead TQFP with multiple approaches to generate the devices system clock. Integrated 1024 word 32-bit RAM The AD9954 is specified to operate over the extended industrial PLL-based REFCLK multiplier temperature range (see Table 2). Internal oscillator, can be driven by a single crystal Phase modulation capability Multichip synchronization APPLICATIONS Agile LO frequency synthesis Programmable clock generators FM chirp source for radar and scanning systems Automotive radars Test and measurement equipment Acousto-optic device drivers BASIC BLOCK DIAGRAM AD9954 DIGITAL 14-BIT SINE DAC 400MSPS WAVE DDS CORE COMPARATOR REF CLOCK TIMING AND INPUT CIRCUITRY CONTROL USER INTERFACE Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20032017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 03374-038AD9954 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Interface Port Pin Descriptions ..................................... 24 Applications ....................................................................................... 1 MSB/LSB Transfers .................................................................... 24 General Description ......................................................................... 1 RAM I/O via Serial Port ............................................................ 24 Basic Block Diagram ........................................................................ 1 Instruction Byte .......................................................................... 25 Revision History ............................................................................... 2 Register Maps and Descriptions ............................................... 25 Functional Block Diagram .............................................................. 3 Control Register Bit Descriptions ............................................ 29 Electrical Specifications ................................................................... 4 Other Register Descriptions ..................................................... 31 Absolute Maximum Ratings ............................................................ 7 Layout Considerations ............................................................... 32 Explanation of Test Levels ........................................................... 7 Detailed Programming Examples ................................................ 33 ESD Caution .................................................................................. 7 Single-Tone Mode ...................................................................... 33 Pin Configuration and Function Descriptions ............................. 8 Linear Sweep Mode .................................................................... 33 Typical Performance Characteristics ........................................... 10 RAM Mode.................................................................................. 33 Theory of Operation ...................................................................... 13 Suggested Application Circuits ..................................................... 35 Component Blocks ..................................................................... 13 Evaluation Board Schematics........................................................ 36 Modes of Operation ................................................................... 16 Outline Dimensions ....................................................................... 39 SynchronizationRegister Updates (I/O UPDATE) ............ 21 Ordering Guide .......................................................................... 39 Serial Port Operation ................................................................. 23 REVISION HISTORY 2/2017Rev. B to Rev. C Changes to Modes of Operation Section and Table 8 ............... 16 Changes to Features Section............................................................ 1 Changes to Table 9 .......................................................................... 17 Changes to Synchronization Register Updates (I/O UPDATE) 5/2009Rev. A to Rev. B Section and Figure 24..................................................................... 21 Changes to Figure 29 and Figure 30 ............................................. 24 Changes to Serial Port Operation Section .................................. 23 Changes to Table 12 ........................................................................ 26 Changes to Serial Interface Port Pin Description Section, Changes to Figure 34 ...................................................................... 35 MSB/LSB Transfers Section, and RAM I/O Via Serial Port Updated Outline Dimensions ....................................................... 39 Section .............................................................................................. 24 Inserted Figure 29 and Figure 30 Renumbered Sequentially .. 24 Changes to Ordering Guide .......................................................... 39 Changes to Instruction Byte Section, Register Maps and 1/2007Rev. 0 to Rev. A Descriptions Section, and Table 12 .............................................. 25 Changes to Layout .............................................................. Universal Changes to Table 13 ....................................................................... 26 Changes to Features, General Description, and Figure 1 ............ 1 Changes to Table 14 ....................................................................... 28 Changes to Figure 2 .......................................................................... 3 Added Single-Tone Mode Section, Linear Sweep Mode Section, Changes to Table 1 ............................................................................ 4 Table 15, and RAM Mode Section ............................................... 33 Changes to Table 4 ............................................................................ 8 Added, and Table 16 ....................................................................... 34 Inserted Figure 35 ........................................................................... 36 Changes to Figure 5 to Figure 10 .................................................. 10 Changes to Figure 12 ...................................................................... 11 Inserted Figure 36 ........................................................................... 37 Changes to Figure 17 to Figure 18 Captions ............................... 12 Inserted Figure 37 ........................................................................... 38 Deleted Figure 19 Renumbered Sequentially............................. 12 Updated Outline Dimensions ....................................................... 39 Added Table 5 Renumbered Sequentially .................................. 13 Changes to Ordering Guide .......................................................... 39 Changes to Component Block Section and Table 6 ................... 13 Changes to Figure 20 ...................................................................... 15 10/2003Revision 0: Initial Version Rev. C Page 2 of 40