TM 2.7 GHz DDS-Based AgileRF Synthesizer AD9956 3.3 V supply for I/O and charge pump FEATURES Software controlled power-down 400 MSPS internal DDS clock speed 48-lead LFCSP package 48-bit frequency tuning word Automatic linear frequency sweeping capability (in DDS) 14-bit programmable phase offset Programmable charge pump current (up to 4 mA) Integrated 14-bit DAC Phase modulation capability Excellent dynamic performance Multichip synchronization Phase noise 135 dBc/Hz 1 KHz offset Dual-mode PLL lock detect 80 dB SFDR 160 MHz (100 KHz offset IOUT) 655 MHz CML-mode PECL-compliant driver 25 Mb/s write-speed serial I/O control APPLICATIONS 200 MHz phase frequency detector inputs 655 MHz programmable input dividers for the phase Agile LO frequency synthesis frequency detector (M, N) M, N = 1..16 (bypassable) FM chirp source for radar and scanning systems Programmable RF divider (R) R = 1, 2, 4, 8 (bypassable) Automotive radars 8 phase/frequency profiles Test and measurement equipment 1.8 V supply for device operation Acousto-optic device drivers FUNCTIONAL BLOCK DIAGRAM DAC RSET DELTA DDS CORE PHASE 48 FREQUENCY OFFSET TUNING WORD PHASE TO IOUT 19 14 AMPLITUDE DAC FREQUENCY CONVERSION ACCUMULATOR IOUT PHASE ACCUMULATOR DELTA FTW PHASE FREQUENCY 48 OFFSET RAMP RATE 14 24 16 WORD SYSCLK SYSCLK PLL LOCK/SYNC IN TIMING AND CONTROL LOGIC I/O RESET I/O UPDATE LOCK OSCILLATOR CHARGE SYSCLK SYNC CLK DETECT PUMP SYNC OUT 4 SCALER RF-DIVIDER R M 3 REFCLK REFCLK BUFFER CHARGE CP OUT PUMP CML CLOCK DRIVER 3 N BUFFER FROM PLLOSC DRV DRV DRV RSET PS<2:0> RESET I/O PORT PLLREF/ PLLOSC/ CP RSET PLLREF PLLOSC Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 20042020 Analog Devices, Inc. All rights reserved. 04806-0-001AD9956 TABLE OF CONTENTS Product Overview ............................................................................. 3 CML Driver ................................................................................. 19 Specifications .................................................................................... 4 Modes of Operation ....................................................................... 20 Loop Measurement Conditions ................................................. 9 DDS Modes of Operation ......................................................... 20 Absolute Maximum Ratings ......................................................... 10 Synchronization Modes for Multiple Devices ............................. 20 ESD Caution................................................................................ 10 Serial Port Operation ..................................................................... 22 Pin Configuration and Function Descriptions .......................... 11 Instruction Byte .......................................................................... 23 Typical Performance Characteristics ........................................... 13 Serial Interface Port Pin Description ...................................... 23 Typical Application Circuits ......................................................... 16 MSB/LSB Transfers .................................................................... 23 Application Circuit Explanations ............................................ 17 Register Map and Description ...................................................... 24 General Description ....................................................................... 18 Control Function Register Descriptions ................................. 27 DDS Core .................................................................................... 18 Outline Dimensions ....................................................................... 32 PLL Circuitry .............................................................................. 18 Ordering Guide .......................................................................... 32 REVISION HISTORY 8/2020Rev. A to Rev. B Changes to Figure 3 ........................................................................ 11 Updated Outline Dimensions ....................................................... 32 Changes to Ordering Guide .......................................................... 32 9/2004Rev. 0 to Rev. A Changes to the Pin Configuration ............................................... 11 Changes to the Pin Function Descriptions ................................. 12 Changes to Table 5 ......................................................................... 24 Changes to CFR2<15:12> PLLREF Divider Control Bits (N) ........................................................................... 31 Changes to CFR2<11:8> PLLREF Divider Control Bits (M) ........................................................................... 31 Changes to Ordering Guide .......................................................... 32 7/2004Revision: Initial Version Rev. B Page 2 of 32