2-Channel, 500 MSPS DDS with 10-Bit DACs Data Sheet AD9958 FEATURES APPLICATIONS 2 synchronized DDS channels 500 MSPS Agile local oscillators Independent frequency/phase/amplitude control between Phased array radars/sonars channels Instrumentation Matched latencies for frequency/phase/amplitude changes Synchronized clocking Excellent channel-to-channel isolation (>72 dB) RF source for AOTF Linear frequency/phase/amplitude sweeping capability Single-side band suppressed carriers Up to 16 levels of frequency/phase/amplitude modulation Quadrature communications (pin-selectable) 2 integrated 10-bit digital-to-analog converters (DACs) Individually programmable DAC full-scale currents 0.12 Hz or better frequency tuning resolution 14-bit phase offset resolution 10-bit output amplitude scaling resolution Serial I/O port interface (SPI) with 800 Mbps data throughput Software-/hardware-controlled power-down Dual supply operation (1.8 V DDS core/3.3 V serial I/O) Multiple device synchronization Selectable 4 to 20 REFCLK multiplier (PLL) Selectable REFCLK crystal oscillator 56-lead LFCSP FUNCTIONAL BLOCK DIAGRAM 10-BIT RECONSTRUCTED AD9958 (2) DAC SINE WAVE 500MSPS 10-BIT RECONSTRUCTED DDS CORES DAC SINE WAVE MODULATION CONTROL SYSTEM TIMING AND REF CLOCK CLOCK CONTROL INPUT CIRCUITRY SOURCE USER INTERFACE Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20052016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 05252-000AD9958 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Linear Sweep Mode .................................................................... 25 Applications ....................................................................................... 1 Linear Sweep No-Dwell Mode ................................................. 26 Functional Block Diagram .............................................................. 1 Sweep and Phase Accumulator Clearing Functions .............. 27 Revision History ............................................................................... 2 Output Amplitude Control Mode ............................................ 28 General Description ......................................................................... 3 Synchronizing Multiple AD9958 Devices ................................... 29 Specifications ..................................................................................... 4 Automatic Mode Synchronization ........................................... 29 Absolute Maximum Ratings ............................................................ 8 Manual Software Mode Synchronization ................................ 29 ESD Caution .................................................................................. 8 Manual Hardware Mode Synchronization .............................. 29 Pin Configuration and Function Descriptions ............................. 9 I/O UPDATE, SYNC CLK, and System Clock Relationships ............................................................................... 30 Typical Performance Characteristics ........................................... 11 Serial I/O Port ................................................................................. 31 Application Circuits ....................................................................... 14 Overview ..................................................................................... 31 Equivalent Input and Output Circuits ......................................... 17 Instruction Byte Description .................................................... 32 Theory of Operation ...................................................................... 18 Serial I/O Port Pin Description ................................................ 32 DDS Core ..................................................................................... 18 Serial I/O Port Function Description ...................................... 32 Digital-to-Analog Converter .................................................... 18 MSB/LSB Transfer Description ................................................ 32 Modes of Operation ....................................................................... 19 Serial I/O Modes of Operation ................................................. 33 Channel Constraint Guidelines ................................................ 19 Register Maps and Bit Descriptions ............................................. 36 Power Supplies ............................................................................ 19 Register Maps .............................................................................. 36 Single-Tone Mode ...................................................................... 19 Descriptions for Control Registers .......................................... 39 Reference Clock Modes ............................................................. 20 Descriptions for Channel Registers ......................................... 41 Scalable DAC Reference Current Control Mode ................... 21 Outline Dimensions ....................................................................... 44 Power-Down Functions ............................................................. 21 Ordering Guide .......................................................................... 44 Modulation Mode ....................................................................... 21 Modulation Using SDIO x Pins for RU/RD .......................... 24 REVISION HISTORY 11/2016Rev. B to Rev. C Change to Figure 35 ....................................................................... 21 Changes to Setting the Slope of the Linear Sweep Section ....... 25 Change to Figure 37 Caption ........................................................ 26 Changes to Figure 37...................................................................... 26 4/2013Rev. A to Rev. B Changes to Figure 38 and Figure 39 ............................................ 27 Changes to Linear Sweep Mode Section and Setting the Slope of Changes to Figure 40...................................................................... 30 the Linear Sweep ............................................................................. 25 Added Table 25 Renumbered Sequentially ................................ 31 Changes to Figure 38 and Figure 39 Captions ............................ 27 Changes to Figure 41...................................................................... 31 Changes to Ramp Rate Timer Section ......................................... 28 Changes to Figure 42, Serial Data I/O (SDIO 0, SDIO 1, SDIO 3) Section, and Added Example Instruction Byte Updated Outline Dimensions ....................................................... 44 Section .............................................................................................. 32 7/2008Rev. 0 to Rev. A Added Table 27 ............................................................................... 33 Changes to Features .......................................................................... 1 Changes to Figure 46, Figure 47, Figure 48, and Figure 49 ...... 35 Inserted Figure 1 Renumbered Sequentially ................................ 1 Changes to Register Maps and Bit Descriptions Section and Changes to Input Level Parameter in Table 1 ............................... 4 Added Endnote 2 to Table 28 ........................................................ 36 Added Profile Pin Toggle Rate Parameter in Table 1 ................... 6 Added Endnote 1 to Table 30 ........................................................ 38 Changes to Layout ............................................................................ 8 Added Exposed Pad Notation to Outline Dimensions ............. 44 Changes to Table 3 ............................................................................ 9 Added Equivalent Input and Output Circuits Section .............. 17 9/2005Revision 0: Initial Version Changes to Reference Clock Input Circuitry Section ................ 20 Rev. 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