4-Channel, 500 MSPS DDS with 10-Bit DACs AD9959 FEATURES Software-/hardware-controlled power-down Dual supply operation (1.8 V DDS core/3.3 V serial I/O) 4 synchronized DDS channels 500 MSPS Multiple device synchronization Independent frequency/phase/amplitude control between Selectable 4 to 20 REFCLK multiplier (PLL) channels Selectable REFCLK crystal oscillator Matched latencies for frequency/phase/amplitude changes 56-lead LFCSP package Excellent channel-to-channel isolation (>65 dB) Linear frequency/phase/amplitude sweeping capability APPLICATIONS Up to 16 levels of frequency/phase/amplitude modulation Agile local oscillators (pin-selectable) Phased array radars/sonars 4 integrated 10-bit digital-to-analog converters (DACs) Instrumentation Individually programmable DAC full-scale currents Synchronized clocking 0.12 Hz or better frequency tuning resolution RF source for AOTF 14-bit phase offset resolution 10-bit output amplitude scaling resolution Serial I/O port interface (SPI) with enhanced data throughput FUNCTIONAL BLOCK DIAGRAM RECONSTRUCTED 10-BIT DAC SINE WAVE (4) RECONSTRUCTED 500MSPS 10-BIT DAC SINE WAVE DDS CORES RECONSTRUCTED 10-BIT DAC SINE WAVE MODULATION CONTROL RECONSTRUCTED 10-BIT DAC SYSTEM TIMING AND SINE WAVE REF CLOCK CLOCK CONTROL INPUT CIRCUITRY SOURCE USER INTERFACE Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20052008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05246-101AD9959 TABLE OF CONTENTS Linear Sweep Mode .................................................................... 25 Features .............................................................................................. 1 Linear Sweep No-Dwell Mode ................................................. 26 Applications ....................................................................................... 1 Sweep and Phase Accumulator Clearing Functions .............. 27 Functional Block Diagram .............................................................. 1 Output Amplitude Control Mode ............................................ 28 General Description ......................................................................... 3 Synchronizing Multiple AD9959 Devices ................................... 29 Specif icat ions ..................................................................................... 4 Automatic Mode Synchronization ........................................... 29 Absolute Maximum Ratings ............................................................ 8 Manual Software Mode Synchronization ................................ 29 ESD Caution .................................................................................. 8 Manual Hardware Mode Synchronization .............................. 29 Pin Configuration and Function Descriptions ............................. 9 I/O UPDATE, SYNC CLK, and System Clock Typical Performance Characteristics ........................................... 11 Relationships ............................................................................... 30 Application Circuits ....................................................................... 14 Serial I/O Port ................................................................................. 31 Equivalent Input and Output Circuits ......................................... 17 Overview ..................................................................................... 31 Theory of Operation ...................................................................... 18 Instruction Byte Description .................................................... 32 DDS Core ..................................................................................... 18 Serial I/O Port Pin Description ................................................ 32 Digital-to-Analog Converter .................................................... 18 Serial I/O Port Function Description ...................................... 32 Modes of Operation ....................................................................... 19 MSB/LSB Transfer Description ................................................ 32 Channel Constraint Guidelines ................................................ 19 Serial I/O Modes of Operation ................................................. 33 Power Supplies ............................................................................ 19 Register Maps and Bit Descriptions ............................................. 36 Single-Tone Mode ...................................................................... 19 Register Maps .............................................................................. 36 Reference Clock Modes ............................................................. 20 Descriptions for Control Registers .......................................... 39 Scalable DAC Reference Current Control Mode ................... 21 Descriptions for Channel Registers ......................................... 41 Power-Down Functions ............................................................. 21 Outline Dimensions ....................................................................... 44 Modulation Mode ....................................................................... 21 Ordering Guide .......................................................................... 44 Modulation Using SDIO x Pins for RU/RD........................... 24 REVISION HISTORY 7/08Rev. A to Rev. B Added Equivalent Input and Output Circuits Section .............. 17 Added Pin Profile Toggle Rate Parameter in Table 1 ................... 6 Changes to Figure 35 ...................................................................... 21 Changes to Figure 24 ...................................................................... 14 Changes to Setting the Slope of the Linear Sweep Section ....... 25 Changes to Figure 31 ...................................................................... 17 Changes to Frequency Linear Sweep Example: AFP Bits = 10 Changes to Reference Clock Input Circuitry Section ................ 20 S ection .............................................................................................. 26 Changes to Operation Section ...................................................... 29 Changes to Figure 37 ...................................................................... 26 Changes to Figure 40 ...................................................................... 30 Changes to Figure 38 and Figure 39............................................. 27 Changes to Serial Data I/O (SDIO 0, SDIO 1, SDIO 3) Added Table 25 ............................................................................... 31 Section .............................................................................................. 32 Changes to Figure 41 ...................................................................... 31 Changes to Table 38 ........................................................................ 43 Changes to Figure 42 ...................................................................... 32 Added Exposed Pad Notation to Outline Dimensions ............. 44 Added Example Instruction Byte Section ................................... 32 Added Table 27 ............................................................................... 33 3/08Rev. 0 to Rev. A Changes to Figure 46, Figure 47, Figure 48, and Figure 49....... 35 Changes to Features .......................................................................... 1 Changes to Register Maps and Bit Descriptions Section .......... 36 Inserted Figure 1 ............................................................................... 1 Added Endnote 1 to Table 30 ........................................................ 38 Changes to Input Level Specification ............................................. 4 Changes to Ordering Guide .......................................................... 44 Changes to Layout ............................................................................ 8 7/05Revision 0: Initial Version Changes to Table 3 ............................................................................ 9 Rev. B Page 2 of 44