Ultralow Distortion Current Feedback Differential ADC Driver Data Sheet ADA4927-1/ADA4927-2 FEATURES FUNCTIONAL BLOCK DIAGRAMS ADA4927-1 Extremely low harmonic distortion 105 dBc HD2 at 10 MHz 91 dBc HD2 at 70 MHz 87 dBc HD2 at 100 MHz FB 1 12 PD 103 dBc HD3 at 10 MHz +IN 2 11 OUT 98 dBc HD3 at 70 MHz IN 3 10 +OUT 89 dBc HD3 at 100 MHz +FB 4 9 V OCM Better distortion at higher gains than VF amplifiers Low input voltage noise: 1.4 nV/Hz High speed 3 dB bandwidth of 2.3 GHz Figure 1. 0.1 dB gain flatness: 150 MHz Slew rate: 5000 V/s, 25% to 75% Fast 0.1% settling time: 10 ns 1 18 IN1 +OUT1 Low input offset voltage: 0.3 mV typical +FB1 2 17 V OCM1 Externally adjustable gain 16 +V 3 V S1 S2 ADA4927-2 Stability and bandwidth controlled by feedback resistor 15 V +V 4 S1 S2 FB2 5 14 PD2 Differential-to-differential or single-ended-to-differential +IN2 6 13 OUT2 operation Adjustable output common-mode voltage Wide supply operation: +5 V to 5 V APPLICATIONS Figure 2. 40 ADC drivers V , = 2V p-p OUT dm 50 Single-ended-to-differential converters IF and baseband gain blocks 60 Differential buffers 70 Differential line drivers 80 GENERAL DESCRIPTION 90 The ADA4927 is a low noise, ultralow distortion, high speed, 100 current feedback differential amplifier that is an ideal choice for driving high performance ADCs with resolutions up to 16 bits G = 1 110 G = 10 from dc to 100 MHz. The output common-mode level can easily be G = 20 120 matched to the required ADC input common-mode levels. The 130 internal common-mode feedback loop provides exceptional output 1 10 100 1k balance and suppression of even-order distortion products. FREQUENCY (MHz) Figure 3. Spurious-Free Dynamic Range vs. Frequency at Various Gains Differential gain configurations are easily realized using an external feedback network comprising four resistors. The The low dc offset and excellent dynamic performance of the current feedback architecture provides loop gain that is nearly ADA4927 make it well suited for a wide variety of data acquisition independent of closed-loop gain, achieving wide bandwidth, and signal processing applications. low distortion, and low noise at higher gains and lower power The ADA4927-1 is available in a Pb-free, 3 mm 3 mm 16-lead consumption than comparable voltage feedback amplifiers. LFCSP, and the ADA4927-2 is available in a Pb-free, 4 mm 4 mm The ADA4927 is fabricated using the Analog Devices, Inc., 24-lead LFCSP. The pinouts are optimized to facilitate printed silicon-germanium complementary bipolar process, enabling circuit board (PCB) layout and to minimize distortion. They are very low levels of distortion with an input voltage noise of only specified to operate over the 40C to +105C temperature range. 1.3 nV/Hz. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20082016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com SPURIOUS-FREE DYNAMIC RANGE (dBc) +V V S S +V V S S V +V S S +V V S S 07574-002 07574-001 07574-026 IN2 7 24 +IN1 5 16 +FB2 8 23 FB1 6 15 +V 9 22 V S2 S1 7 14 21 +V 10 V S2 S1 8 13 V 11 20 PD1 OCM2 +OUT2 12 19 OUT1ADA4927-1/ADA4927-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Definition of Terms .................................................................... 17 Applications ....................................................................................... 1 Applications Information .............................................................. 18 General Description ......................................................................... 1 Analyzing an Application Circuit ............................................ 18 Functional Block Diagrams ............................................................. 1 Setting the Closed-Loop Gain .................................................. 18 Revision History ............................................................................... 2 Estimating the Output Noise Voltage ...................................... 18 Specifications ..................................................................................... 3 Impact of Mismatches in the Feedback Networks ................. 19 5 V Operation ............................................................................. 3 Calculating the Input Impedance for an Application Circuit ....................................................................................................... 19 +5 V Operation ............................................................................. 5 Input Common-Mode Voltage Range ..................................... 21 Absolute Maximum Ratings ............................................................ 7 Input and Output Capacitive AC Coupling ............................ 21 Thermal Resistance ...................................................................... 7 Setting the Output Common-Mode Voltage .......................... 21 Maximum Power Dissipation ..................................................... 7 Power-Down ............................................................................... 22 ESD Caution .................................................................................. 7 Layout, Grounding, and Bypassing .............................................. 23 Pin Configurations and Function Descriptions ........................... 8 High Performance ADC Driving ................................................. 24 Typical Performance Characteristics ............................................. 8 Outline Dimensions ....................................................................... 25 Test Circuits ..................................................................................... 16 Ordering Guide .......................................................................... 25 Theory of Operation ...................................................................... 17 REVISION HISTORY 5/2016Rev. A to Rev. 0 Changes to Figure 1 and Figure 2 ................................................... 1 Changes to Figure 5 .......................................................................... 8 Changes to Figure 6 .......................................................................... 9 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 25 8/2009Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 24 10/2008Revision 0: Initial Version Rev. B Page 2 of 25