10 GHz to 40 GHz, 4-Channel Rx Mixer with 4 LO Multiplier/Filter Data Sheet ADAR2004 FEATURES GENERAL DESCRIPTION Quad LNA, mixer, IF VGA The ADAR2004 is a 4-channel receiver IC that is optimized for 4 LO multiplier with programmable harmonic filter millimeter wave body scanning applications. Accepting differential RF input frequency range: 10 GHz to 40 GHz input signals from 10 GHz to 40 GHz, the ADAR2004 provides a IF output frequency range: 0 MHz to 800 MHz low intermediate frequency (IF) output up to 800 MHz. Each LO input frequency range: 2.4 GHz to 10.1 GHz receive channel also has independent gain control. Gain range: 21 dB to 41 dB The mixer local oscillator (LO) path includes a 4 multiplier Input P1dB: 20 dBm typical (at minimum gain) requiring an applied LO frequency between 2.4 GHz and Noise figure: 9 dB typical (at maximum gain) 10.1 GHz. The 4 multiplier block includes a programmable filter 3-wire or 4-wire SPI control that helps keep harmonics down before reaching the mixer. On-chip programmable state machines for fast multiplier/filter and receiver switching and control Two programmable state machines are included to facilitate On-chip temperature sensor and ADC simple configuration, control, and fast switching of the frequency DC power: 910 mW (2.5 V supply) multiplier, filter, and receiver sections. These sequencers are 7 mm 7 mm, 48-terminal LGA package programmed through the serial peripheral interface (SPI) and are then operated by pulsed inputs (reset and advance). APPLICATIONS Millimeter wave imaging The ADAR2004 requires only a single 2.5 V supply with power Security consumption of 910 mW with all channels turned on. Medical The ADAR2004 is available in a 7 7 mm, 48-terminal LGA Industrial package and is specified from 40C to +85C. Multichannel receivers FUNCTIONAL BLOCK DIAGRAM ADAR2004 RECEIVER SEQUENCER RFIN1+ IFOUT1+ LNA VGA RFIN1 IFOUT1 RFIN2+ IFOUT2+ LNA VGA RFIN2 IFOUT2 RFIN3+ IFOUT3+ LNA VGA RFIN3 IFOUT3 RFIN4+ IFOUT4+ LNA VGA RFIN4 IFOUT4 MULTIPLIER/FILTER SEQUENCER 4 LOIN BUFFER 4 4 CS SDIO SPI ADC CONTROL SCLK SDO TEMPERATURE SENSOR MULTIPLIER/FILTER RECEIVER STATE MACHINE STATE MACHINE (16 STATES) (16 STATES) MRST MADV RxRST RxADV Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 2020 Analog Devices, Inc. All rights reserved. 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Trademarks and registered trademarks are the property of their respective owners. 20539-001ADAR2004 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ADC and ADC Clock ................................................................ 17 Applications ...................................................................................... 1 Applications Information ............................................................. 18 General Description ......................................................................... 1 SPI Control .................................................................................. 18 Functional Block Diagram .............................................................. 1 State Machine Modes vs. States ................................................ 18 Revision History ............................................................................... 2 State Machine Setup .................................................................. 18 Specifications .................................................................................... 3 Multiplier/Filter State Machine ................................................ 19 Timing Specifications .................................................................. 5 Receiver State Machine ............................................................. 19 Absolute Maximum Ratings ........................................................... 7 Frequency Sweep All Channels ................................................ 20 Thermal Resistance ...................................................................... 7 Sequencer Sleep Control ........................................................... 20 Electrostatic Discharge (ESD) Ratings ...................................... 7 Sequencer Sleep Hold ................................................................ 21 ESD Caution.................................................................................. 7 Sequencer Control Latch Bypass .............................................. 21 Pin Configuration and Function Descriptions ............................ 8 Parallel Chip Control ................................................................. 22 Typical Performance Characteristics ........................................... 10 Multichip Frequency Sweep ..................................................... 22 Theory of Operation ...................................................................... 16 Bias Points and Voltages ............................................................... 24 Overview ...................................................................................... 16 Register Summary .......................................................................... 25 LO Input Buffer, 4 Multiplier, and Band-Pass Filter .......... 16 Outline Dimensions ....................................................................... 37 1:4 Signal Splitter Network ....................................................... 16 Ordering Guide .......................................................................... 37 Receivers ...................................................................................... 17 Temperature Sensor ................................................................... 17 REVISION HISTORY 8/2020Revision 0: Initial Version Rev. 0 Page 2 of 37