4-Channel, 16-Bit, Continuous Time Data Acquisition ADC Data Sheet ADAR7251 FEATURES GENERAL DESCRIPTION Low noise: 2.4 nV/Hz input referred voltage noise at The ADAR7251 is a 16-bit, 4-channel, simultaneous sampling maximum gain setting analog-to-digital converter (ADC) designed especially for Wide input signal bandwidth: 500 kHz at 1.2 MSPS sample applications such as automotive LSR-FMCW or FSK-FMCW rate, 16-bit resolution radar systems. Each of the four channels contains a low noise Additional sample rates supported: 300 kSPS, 450 kSPS, amplifier (LNA), a programmable gain amplifier (PGA), an 600 kSPS, 900 kSPS, and 1.8 MSPS equalizer, a multibit - ADC, and a decimation filter. 4 differential simultaneous sampling channels The front-end circuitry is designed to allow direct connection No active antialiasing filter required to an MMIC output with few external passive components. The LNA and PGA with 45 dB gain range in 6 dB steps ADAR7251 eliminates the need for a high order antialiasing Selectable equalizer filter, driver op amps, and external bipolar supplies. The Flexible data port supports serial or parallel mode ADAR7251 also offers precise channel-to-channel drift Supports FSK mode for FMCW radar systems matching. On-chip 1.5 V reference The ADAR7251 features an on-chip phase-locked loop (PLL) Internal oscillator/PLL input: 16 MHz to 54 MHz that allows a range of clock frequencies for flexibility in the system. High speed serial data interface CONV START The input and DATA READY output signals SPI control synchronize the ADC with an external ramp for applications such 2 general-purpose inputs/outputs as FSK-FMCW radar. 48-lead LFCSP SS package Temperature range: 40C to +125C The ADAR7251 supports serial and parallel interfaces at Single supply operation of 3.3 V programmable sample rates from 300 kSPS to 1.8 MSPS, as well Qualified for automotive applications as easy connections to digital signal processors (DSPs) and microcontroller units (MCUs) in the system. APPLICATIONS Automotive LSR systems Data acquisition systems Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. ADAR7251 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 PLL Control Register ................................................................. 38 Applications ....................................................................................... 1 PLL Status Register ..................................................................... 38 General Description ......................................................................... 1 Master Enable Switch Register ................................................. 39 Revision History ............................................................................... 3 ADC Enable Register ................................................................. 39 Functional Block Diagram .............................................................. 4 Power Enable Register ............................................................... 40 Specif icat ions ..................................................................................... 5 Clear the ASIL errors Register .................................................. 41 Analog Channel ............................................................................ 5 Selects Which Errors to Mask Register ................................... 42 Digital Input/Output .................................................................... 6 ASIL Error Flag Register ........................................................... 43 Power Supply ................................................................................. 7 ASIL Error Code Register ......................................................... 43 Digital Filter .................................................................................. 8 CRC Value, Bits 7:0 Register ................................................... 44 SPI Port Timing ............................................................................ 8 CRC Value Register .................................................................... 44 Serial/Peripheral Parallel Interface (PPI) Port Timing............ 8 Start Calculating the CRC Value of the Register Map Content Register ........................................................................................ 45 Absolute Maximum Ratings .......................................................... 11 Register Map CRC Calculation Done Register ...................... 45 Thermal Resistance .................................................................... 11 Register Map CRC Value, Bits 7:0 Register ........................... 45 ESD Caution ................................................................................ 11 Register Map CRC Value, Bits 15:8 Register ......................... 46 Pin Configuration and Function Descriptions ........................... 12 Low Noise Amplifier Gain Control Register .......................... 46 Typical Performance Characteristics ........................................... 14 Programmable Gain Amplifier Gain Control Register ......... 47 Terminology .................................................................................... 17 Signal Path for ADC 1 Through ADC 4 Register .................. 48 Theory of Operation ...................................................................... 18 Decimator Rate Control Register ............................................. 49 Low Speed Ramp Radar Analog Front End ............................ 18 High Pass Filter Control Register ............................................. 50 Main Channel Overview ........................................................... 18 DAQ Mode Control Register .................................................... 51 - Modulation and Digital Filtering ..................................... 18 Decimator Truncate Control Register ..................................... 52 Differential Input Configuration .............................................. 19 Serial Output Port Control Register ........................................ 52 Equalizer (EQ) ............................................................................ 19 Parallel Port Control Register ................................................... 53 Using LNA/PGA, EQ, or the Input Capacitor ........................ 20 ADC Digital Output Mode Register ........................................ 54 Reference ..................................................................................... 20 Auxiliary ADC Read Value Registers ...................................... 54 Auxiliary ADC ............................................................................ 20 Auxiliary ADC Sample Rate Selection Register ..................... 55 Power Supply ............................................................................... 21 Auxiliary ADC Mode Register ................................................. 56 LDO .............................................................................................. 21 MPx Pin Modes Registers ......................................................... 56 Clock Requirements ................................................................... 21 MP Write Value Registers .......................................................... 58 Crystal Oscillator ........................................................................ 21 MP Read Value Registers........................................................... 58 PLL ............................................................................................... 21 SPI CLK Pin Drive Strength and Slew Rate Register ........... 59 GPIO ............................................................................................ 23 SPI MISO Pin Drive Strength and Slew Rate Register ......... 60 ADC Data Port ........................................................................... 23 SPI SS Pin Drive Strength and Slew Rate Register ............... 60 PCB Layout Guidelines .................................................................. 33 SPI MOSI Pin Drive Strength and Slew Rate Register ......... 61 Register Summary .......................................................................... 34 ADDR15 Pin Drive Strength and Slew Rate Register ........... 62 Register Details ............................................................................... 37 FAULT Pin Drive Strength and Slew Rate Register ............... 62 Clock Control Register .............................................................. 37 FS ADC Pin Drive Strength and Slew Rate Register ............ 63 PLL Denominator Register ....................................................... 37 CONV START Pin Drive Strength and Slew Rate Register ..... 64 PLL Numerator Register ............................................................ 37 Rev. 0 Page 2 of 72