1.25 GHz Dual Integrated DCL with PPMU, Level Setting DACs, and On-Chip Calibration Registers Data Sheet ADATE320 FEATURES GENERAL DESCRIPTION 1.25 GHz, 2.5 Gbps data rate The ADATE320 is a complete, single-chip ATE solution that 3-level driver with high-Z and reflection clamps performs the pin electronics functions of a driver, comparator, Window and differential comparators and active load (DCL), and a four quadrant per pin parametric 25 mA active load measurement unit (PPMU). Dedicated 16-bit digital-to-analog Per pin parametric measurement unit (PMU) with a 1.5 V to converters (DACs) with on-chip calibration registers provide all +4.5 V range the necessary dc levels for operation of the device. Low leakage mode (typically <5 nA) The driver features three active modes: high, low, and terminate, as Integrated 16-bit DACs with offset and gain correction well as a high impedance inhibit state. The inhibit state, in 1.2 W power dissipation per channel (ADATE320) conjunction with the integrated dynamic clamps, facilitates 1.3 W power dissipation per channel (ADATE320-1) significant attenuation of transmission line reflections when the Driver driver is not actively terminating the line. The open-circuit drive Voltage range: 1.5 V to +4.5 V capability is 1.5 V to +4.5 V to accommodate a standard range Precision trimmed termination: 50.0 of ATE and instrumentation applications. Unterminated swing: 50 mV minimum to 6.0 V maximum The ADATE320 can be used as a dual, single-ended pin 400 ps minimum pulse width, 1.0 V programmed swing electronics channel or as a single differential channel. In 25 ps deterministic jitter addition to per channel high speed window comparators, the Comparator ADATE320 provides a programmable threshold differential Differential and single-ended window modes comparator for differential ATE applications. 100 ps equivalent input rise/fall time (ERT/EFT) 250 mV current mode logic (CML) outputs (ADATE320) All dc levels for DCL and PPMU functions are generated by 400 mV CML outputs (ADATE320-1) dedicated, on-chip, 16-bit DACs. To facilitate the programming Load of accurate levels, the ADATE320 includes an integrated Per pin PMU (PPMU) calibration function to correct for the gain and offset errors of Force voltage/compliance range: 1.5 V to +4.5 V each functional block. Correction coefficients can be stored on 5 current ranges chip, and any values written to the DACs adjust automatically 40 mA, 1 mA, 100 A, 10 A, 2 A using the appropriate correction factors. Dedicated go/no-go comparators The ADATE320 uses a serial programmable interface (SPI) bus DC levels to program all functional blocks, DACs, and on-chip calibration Fully integrated and dedicated 16-bit DACs constants. It also has an on-chip temperature sensor and overvolt- On-chip gain and offset calibration registers with age/undervoltage fault clamps that monitor and report the automatic add/multiply function device temperature and any output pin or transient PPMU 84-lead, 10 mm 10 mm LFCSP (0.4 mm pitch) voltage faults that may occur during operation. APPLICATIONS The ADATE320 is available in two options. The standard option Automatic test equipment (ATE) has high speed comparator outputs with 250 mV output swing. Semiconductor/board test systems The ADATE320-1 has 400 mV output swing. See the Ordering Instrumentation and characterization equipment Guide for more information. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20152016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com ADATE320 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Characteristics ............................................................ 25 Applications ....................................................................................... 1 Explanation of Test Levels ......................................................... 25 General Description ......................................................................... 1 ESD Caution................................................................................ 25 Revision History ............................................................................... 2 User Information and Truth Tables ......................................... 26 Functional Block Diagram .............................................................. 3 Pin Configuration and Function Descriptions ........................... 28 Specifications ..................................................................................... 4 Typical Performance Characteristics ........................................... 30 Electrical Specifications ............................................................... 4 Theory of Operation ...................................................................... 50 Driver Specifications .................................................................... 5 Serial Programmable Interface (SPI) ....................................... 50 Reflection Clamp Specifications ................................................. 7 Level Setting DACs .................................................................... 52 Normal Window Comparator (NWC) Specifications ............. 8 Alarm Functions ......................................................................... 59 Differential Mode Comparator (DMC) Specifications ......... 10 Applications Information .............................................................. 62 Active Load Specifications ........................................................ 11 Power Supply, Grounding, and Typical Decoupling Strategy ....................................................................................................... 62 PPMU Specifications ................................................................. 13 Power Supply Sequencing ......................................................... 64 PPMU Go/No-Go Comparators Specifications ..................... 18 Detailed Functional Block Diagrams ........................................... 65 PPMU External Sense Pins Specifications .............................. 18 SPI Register Memory Map and Details ....................................... 71 VREF, VREFGND, and DUTGND Reference Input Pins Specifications .............................................................................. 19 Memory Map .............................................................................. 71 Temperature Monitor Specifications ....................................... 19 Register Details ........................................................................... 74 Alarm Functions Specifications................................................ 19 Default Test Conditions ................................................................. 80 Serial Programmable Interface (SPI) Specifications .............. 20 External Components .................................................................... 81 SPI Timing Specifications ......................................................... 20 Outline Dimensions ....................................................................... 82 SPI Timing Diagrams ................................................................. 21 Ordering Guide .......................................................................... 82 Absolute Maximum Ratings .......................................................... 25 REVISION HISTORY 9/2016Rev. A to Rev. B Changes to Time Constant 1 Parameter and Time Constant 2 Parameter, Table 2 ............................................................................. 7 Changes to IOx Offset Parameter, and IOHx Offset Parameter, Table 6 ........................................................................... 11 Change to AGND Pin Number Column ..................................... 29 RST Change to SPI Reset Sequence and the Pin Section .......... 50 BUSY Changes to the SPI Clock Cycles and Pin Section .......... 51 Changes to Table 24 ........................................................................ 54 Changes to Figure 137 .................................................................... 65 10/2015Revision A: Initial Version Rev. B Page 2 of 82