Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL Data Sheet ADAU1361 FEATURES GENERAL DESCRIPTION 24-bit stereo audio ADC and DAC: >98 dB SNR The ADAU1361 is a low power, stereo audio codec that supports Sampling rates from 8 kHz to 96 kHz stereo 48 kHz record and playback at 14 mW from a 1.8 V analog Low power: 7 mW record, 7 mW playback, 48 kHz at 1.8 V supply. The stereo audio ADCs and DACs support sample rates 6 analog input pins, configurable for single-ended or from 8 kHz to 96 kHz as well as a digital volume control. The differential inputs ADAU1361 is ideal for battery-powered audio and telephony Flexible analog input/output mixers applications. Stereo digital microphone input The record path includes an integrated microphone bias circuit Analog outputs: 2 differential stereo, 2 single-ended stereo, and six inputs. The inputs can be mixed and muxed before the 1 mono headphone output driver ADC, or they can be configured to bypass the ADC. The PLL supporting input clocks from 8 MHz to 27 MHz ADAU1361 includes a stereo digital microphone input. Analog automatic level control (ALC) The ADAU1361 includes five high power output drivers (two Microphone bias reference voltage differential and three single-ended), supporting stereo head- Analog and digital I/O: 1.8 V to 3.65 V 2 phones, an earpiece, or other output transducer. AC-coupled I C and SPI control interfaces or capless configurations are supported. Individual fine level Digital audio serial data I/O: stereo and time-division controls are supported on all analog outputs. The output mixer multiplexing (TDM) modes stage allows for flexible routing of audio. Software-controllable clickless mute 2 Software power-down The serial control bus supports the I C and SPI protocols. The 2 32-lead, 5 mm 5 mm LFCSP serial audio bus is programmable for I S, left-/right-justified, 40C to +85C operating temperature range and TDM modes. A programmable PLL supports flexible clock generation for all standard integer rates and fractional master APPLICATIONS clocks from 8 MHz to 27 MHz. Smartphones/multimedia phones Digital still cameras/digital video cameras Portable media players/portable audio players Phone accessories products FUNCTIONAL BLOCK DIAGRAM HP JACK REGULATOR ADAU1361 JACKDET/MICIN DETECTION LAUX LOUTP LINP LOUTN DAC ADC LHP INPUT LINN ADC DAC MIXERS OUTPUT MONOOUT DIGITAL DIGITAL MIXERS RINP FILTERS FILTERS ALC RHP ADC DAC RINN ROUTP ROUTN RAUX 2 MICROPHONE SERIAL DATA I C/SPI MICBIAS PLL BIAS INPUT/OUTPUT PORTS CONTROL PORT MCLK ADC SDATA DAC SDATA ADDR0/ ADDR1/ SCL/ SDA/ CDATA CCLK COUT CLATCH Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20092018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. CM IOVDD BCLK LRCLK DGND DVDDOUT AVDD AVDD AGND AGND 07679-001ADAU1361 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Core Clock ................................................................................... 26 Applications ....................................................................................... 1 Sampling Rates ............................................................................ 26 General Description ......................................................................... 1 PLL ............................................................................................... 27 Functional Block Diagram .............................................................. 1 Record Signal Path ......................................................................... 29 Revision History ............................................................................... 3 Input Signal Paths ....................................................................... 29 Specifications ..................................................................................... 4 Analog-to-Digital Converters ................................................... 31 Analog Performance Specifications ........................................... 4 Automatic Level Control (ALC) ................................................... 32 Power Supply Specifications........................................................ 7 ALC Parameters .......................................................................... 32 Typical Current Consumption .................................................... 8 Noise Gate Function .................................................................. 33 Typical Power Management Measurements ............................. 9 Playback Signal Path ...................................................................... 35 Digital Filters ............................................................................... 10 Output Signal Paths ................................................................... 35 Digital Input/Output Specifications......................................... 10 Headphone Output .................................................................... 36 Digital Timing Specifications ................................................... 11 Pop-and-Click Suppression ...................................................... 37 Digital Timing Diagrams........................................................... 12 Line Outputs ............................................................................... 37 Absolute Maximum Ratings .......................................................... 14 Control Ports ................................................................................... 38 Thermal Resistance .................................................................... 14 Burst Mode Writing and Reading ............................................ 38 2 ESD Caution ................................................................................ 14 I C Port ........................................................................................ 38 Pin Configuration and Function Descriptions ........................... 15 SPI Port ........................................................................................ 41 Typical Performance Characteristics ........................................... 17 Serial Data Input/Output Ports .................................................... 42 System Block Diagrams ................................................................. 20 Applications Information .............................................................. 44 Theory of Operation ...................................................................... 23 Power Supply Bypass Capacitors .............................................. 44 Startup, Initialization, and Power ................................................. 24 GSM Noise Filter ........................................................................ 44 Power-Up Sequence ................................................................... 24 Grounding ................................................................................... 44 Power Reduction Modes ............................................................ 24 Exposed Pad PCB Design ......................................................... 44 Digital Power Supply .................................................................. 24 Control Registers ............................................................................ 45 Input/Output Power Supply ...................................................... 24 Control Register Details ............................................................ 46 Clock Generation and Management ........................................ 24 Outline Dimensions ....................................................................... 79 Clocking and Sampling Rates ....................................................... 26 Ordering Guide .......................................................................... 79 Rev. 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