SigmaDSP Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL ADAU1461 FEATURES GENERAL DESCRIPTION SigmaDSP 28-/56-bit, 50 MIPS digital audio processor The ADAU1461 is a low power, stereo audio codec with Fully programmable with SigmaStudio graphical tool integrated digital audio processing that supports stereo 48 kHz 24-bit stereo audio ADC and DAC: >98 dB SNR record and playback at 35 mW from a 3.3 V analog supply. The Sampling rates from 8 kHz to 96 kHz stereo audio ADCs and DACs support sample rates from 8 kHz Low power: 17 mW record, 18 mW playback, 48 kHz to 96 kHz as well as a digital volume control. 6 analog input pins, configurable for single-ended or The SigmaDSP core features 28-bit processing (56-bit double differential inputs precision). The processor allows system designers to compensate Flexible analog input/output mixers for the real-world limitations of microphones, speakers, amplifiers, Stereo digital microphone input and listening environments, resulting in a dramatic improvement Analog outputs: 2 differential stereo, 2 single-ended stereo, in the perceived audio quality through equalization, multiband 1 mono headphone output driver compression, limiting, and third-party branded algorithms. PLL supporting input clocks from 8 MHz to 27 MHz The SigmaStudio graphical development tool is used to program Analog automatic level control (ALC) the ADAU1461. This software includes audio processing blocks Microphone bias reference voltage such as filters, dynamics processors, mixers, and low level DSP Analog and digital I/O: 3.3 V 2 functions for fast development of custom signal flows. I C and SPI control interfaces Digital audio serial data I/O: stereo and time-division The record path includes an integrated microphone bias circuit multiplexing (TDM) modes and six inputs. The inputs can be mixed and muxed before the Software-controllable clickless mute ADC, or they can be configured to bypass the ADC. The GPIO pins for digital controls and outputs ADAU1461 includes a stereo digital microphone input. 32-lead, 5 mm 5 mm LFCSP The ADAU1461 includes five high power output drivers (two 40C to +105C operating temperature range differential and three single-ended), supporting stereo head- Qualified for automotive applications phones, an earpiece, or other output transducer. AC-coupled APPLICATIONS or capless configurations are supported. Individual fine level controls are supported on all analog outputs. The output mixer Automotive head units stage allows for flexible routing of audio. Automotive amplifiers Navigation systems Rear-seat entertainment systems FUNCTIONAL BLOCK DIAGRAM HP JACK REGULATOR ADAU1461 JACKDET/MICIN DETECTION LAUX LOUTP LINP LOUTN DAC ADC ADC DAC LHP LINN INPUT DIGITAL DIGITAL MIXERS FILTERS FILTERS OUTPUT MONOOUT MIXERS RINP ALC ADC DAC RHP RINN ROUTP ROUTN RAUX 2 MICROPHONE SERIAL DATA I C/SPI MICBIAS PLL BIAS INPUT/OUTPUT PORTS CONTROL PORT MCLK ADDR0/ ADDR1/ SCL/ SDA/ CLATCH CDATA CCLK COUT Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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ADC SDATA/ GPIO1 CM BCLK/ GPIO2 IOVDD DGND LRCLK/ GPIO3 DVDDOUT DAC SDATA/ AVDD GPIO0 AVDD AGND AGND 08914-001ADAU1461 TABLE OF CONTENTS Features .............................................................................................. 1 Playback Signal Path ...................................................................... 33 Applications ....................................................................................... 1 Output Signal Paths ................................................................... 33 General Description ......................................................................... 1 Headphone Output .................................................................... 34 Functional Block Diagram .............................................................. 1 Pop-and-Click Suppression ...................................................... 35 Revision History ............................................................................... 2 Line Outputs ............................................................................... 35 Specif icat ions ..................................................................................... 3 Control Ports ................................................................................... 36 Analog Performance Specifications, T = 25C ....................... 3 Burst Mode Writing and Reading ............................................ 36 A 2 Analog Performance Specifications, 40C < T < +105C ... 5 I C Port ........................................................................................ 36 A Power Supply Specifications........................................................ 7 SPI Port ........................................................................................ 39 Digital Filters ................................................................................. 8 Serial Data Input/Output Ports .................................................... 40 Digital Input/Output Specifications........................................... 8 Applications Information .............................................................. 42 Digital Timing Specifications ..................................................... 9 Power Supply Bypass Capacitors .............................................. 42 Digital Timing Diagrams........................................................... 10 GSM Noise Filter ........................................................................ 42 Absolute Maximum Ratings .......................................................... 12 Grounding ................................................................................... 42 Thermal Resistance .................................................................... 12 Exposed Pad PCB Design ......................................................... 42 ESD Caution ................................................................................ 12 DSP Core ......................................................................................... 43 Pin Configuration and Function Descriptions ........................... 13 Signal Processing ........................................................................ 43 Typical Performance Characteristics ........................................... 15 Architecture ................................................................................ 43 System Block Diagrams ................................................................. 18 Program Counter ....................................................................... 43 Theory of Operation ...................................................................... 21 Features ........................................................................................ 43 Startup, Initialization, and Power ................................................. 22 Startup .......................................................................................... 43 Power-Up Sequence ................................................................... 22 Numeric Formats ....................................................................... 44 Power Reduction Modes ............................................................ 22 Programming .............................................................................. 44 Digital Power Supply .................................................................. 22 Program RAM, Parameter RAM, and Data RAM ..................... 45 Input/Output Power Supply ...................................................... 22 Program RAM ............................................................................ 45 Clock Generation and Management ........................................ 22 Parameter RAM .......................................................................... 45 Clocking and Sampling Rates ....................................................... 24 Data RAM ................................................................................... 45 Core Clock ................................................................................... 24 Read/Write Data Formats ......................................................... 45 Sampling Rates ............................................................................ 25 Software Safeload ....................................................................... 46 PLL ............................................................................................... 25 Software Slew .............................................................................. 47 Record Signal Path .......................................................................... 27 General-Purpose Input/Output .................................................... 48 Input Signal Paths ....................................................................... 27 GPIO Pins Set from the Control Port ...................................... 48 Analog-to-Digital Converters ................................................... 29 Control Registers ............................................................................ 49 Automatic Level Control (ALC) ................................................... 30 Control Register Details ............................................................ 50 ALC Parameters .......................................................................... 30 Outline Dimensions ....................................................................... 88 Noise Gate Function .................................................................. 31 Ordering Guide .......................................................................... 88 Automotive Products ................................................................. 88 REVISION HISTORY 6/10Revision 0: Initial Version Rev. 0 Page 2 of 88