1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer ADCLK854 FEATURES FUNCTIONAL BLOCK DIAGRAM 2 selectable differential inputs ADCLK854 Selectable LVDS/CMOS outputs LVDS/ V /2 S CMOS OUT0 (OUT0A) Up to 12 LVDS (1.2 GHz) or 24 CMOS (250 MHz) outputs V REF OUT0 (OUT0B) <12 mW per channel (100 MHz operation) CLK0 54 fs rms integrated jitter (12 kHz to 20 MHz) OUT1 (OUT1A) CLK0 100 fs rms additive broadband jitter OUT1 (OUT1B) 2.0 ns propagation delay (LVDS) CLK1 OUT2 (OUT2A) CLK1 135 ps output rise/fall (LVDS) OUT2 (OUT2B) 70 ps output-to-output skew (LVDS) IN SEL OUT3 (OUT3A) Sleep mode OUT3 (OUT3B) CTRL A Pin programmable control 1.8 V power supply LVDS/ CMOS OUT4 (OUT4A) APPLICATIONS OUT4 (OUT4B) Low jitter clock distribution OUT5 (OUT5A) Clock and data signal restoration OUT5 (OUT5B) CTRL B Level translation OUT6 (OUT6A) Wireless communications OUT6 (OUT6B) Wired communications Medical and industrial imaging OUT7 (OUT7A) ATE and high performance instrumentation OUT7 (OUT7B) GENERAL DESCRIPTION LVDS/ CMOS OUT8 (OUT8A) The ADCLK854 is a 1.2 GHz/250 MHz LVDS/CMOS fanout OUT8 (OUT8B) buffer optimized for low jitter and low power operation. Possible OUT9 (OUT9A) configurations range from 12 LVDS to 24 CMOS outputs, OUT9 (OUT9B) CTRL C including combinations of LVDS and CMOS outputs. Three control lines are used to determine whether fixed blocks of OUT10 (OUT10A) outputs (three banks of four) are LVDS or CMOS outputs. OUT10 (OUT10B) SLEEP The ADCLK854 offers two selectable inputs and a sleep mode OUT11 (OUT11A) feature. The IN SEL pin state determines which input is fanned OUT11 (OUT11B) out to all the outputs. The SLEEP pin enables a sleep mode to power down the device. Figure 1. The inputs accept various types of single-ended and differential logic levels including LVPECL, LVDS, HSTL, CML, and CMOS. Table 8 provides interface options for each type of connection. This device is available in a 48-pin LFCSP package. It is specified for operation over the standard industrial temperature range of 40C to +85C. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 www.analog.com No license is granted by implication or otherwise under any patent or patent rights of Analog Fax: 781.461.3113 20092020 Analog Devices, Inc. All rights reserved. Devices. Trademarks and registered trademarks are the property of their respective owners. 07218-001ADCLK854 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics .............................................9 Applications ...................................................................................... 1 Functional Description .................................................................. 12 General Description ......................................................................... 1 Clock Inputs ................................................................................ 12 Functional Block Diagram .............................................................. 1 AC-Coupled Input Applications ............................................. 12 Revision History ............................................................................... 2 Clock Outputs ............................................................................. 12 Specifications .................................................................................... 3 Control and Function Pins ....................................................... 13 Electrical Characteristics ............................................................. 3 Power Supply .............................................................................. 13 Timing Characteristics ................................................................ 4 Applications Information ............................................................. 14 Clock Characteristics ................................................................... 5 Using the ADCLK854 Outputs for ADC Clock Applications ....................................................................................................... 14 Logic and Power Characteristics ................................................ 5 LVDS Clock Distribution.......................................................... 14 Absolute Maximum Ratings ........................................................... 6 CMOS Clock Distribution ........................................................ 14 Determining Junction Temperature .......................................... 6 Input Termination Options ...................................................... 15 ESD Caution.................................................................................. 6 Outline Dimensions ....................................................................... 16 Thermal Performance .................................................................. 6 Ordering Guide .......................................................................... 16 Pin Configuration and Function Descriptions ............................ 7 REVISION HISTORY 11/2020Rev. 0 to Rev. A Changed CP-48-6 to CP-48-21 .................................... Throughout Changes to Figure 2 .......................................................................... 7 Updated Outline Dimensions ....................................................... 16 Changes to Ordering Guide .......................................................... 16 4/2009Revision 0: Initial Version Rev. A Page 2 of 16