NB3N511 PLL Clock Multiplier, 14 MHz - 200 MHz, 3.3 V / 5.0 V Description www.onsemi.com The NB3N511 is a clock multiplier that will generate one of nine selectable output multiples of an input frequency via two 3level MARKING DIAGRAM select inputs (S0, S1). It accepts a standard fundamental mode crystal 8 8 or an external reference clock signal. PhaseLockedLoop (PLL) 1 3N511 design techniques are used to produce a low jitter, TTL level clock ALYW SOIC8 output up to 200 MHz with a 50% duty cycle. An Output Enable (OE) D SUFFIX pin is provided, and when asserted low, the clock output goes into tri 1 CASE 751 state (high impedance). The NB3N511 is commonly used in 3N511 = Specific Device Code electronic systems as a cost efficient replacement for crystal A = Assembly Location oscillators L = Wafer Lot Y = Year Features W = Work Week = PbFree Package Clock Output Frequencies up to 200 MHz Nine Selectable Multipliers of the Input Frequency ORDERING INFORMATION Operating Range: V = 3.3 V 10% or 5.0 V 5% DD See detailed ordering and shipping information in the package Low Jitter Output of 25 ps One Sigma (rms) dimensions section on page 5 of this data sheet. Zero ppm Clock Multiplication Error 45% 55% Output Duty Cycle TTL/CMOS Output with 25 mA TTL Level Drive Crystal Reference Input Range of 5 32 MHz Input Clock Frequency Range of 1 50 MHz OE, Output Enable with TriState Output 8Pin SOIC Industrial Temperature Range 40C to +85C These are PbFree Devices V DD X1/ICLK Crystal crystal or TTL/ P Phase Charge clock Oscillator CMOS VCO Detector Pump Output CLKOUT C C LX1 LX2 X2 Multiplier Select Feedback M S1 S0 OE GND Figure 1. NB3N511 Logic Diagram Semiconductor Components Industries, LLC, 2013 1 Publication Order Number: January, 2019 Rev. 5 NB3N511/DNB3N511 Table 1. CLOCK MULTIPLIER SELECT TABLE X1/ICLK 1 8 X2 S1* S0* CLKOUT Multiplier L L 4X Input V DD 2 7 OE L M 5.333X Input GND 3 L H 5X Input 6 S0 M L 2.5X Input S145 CLKOUT M M 2X Input M H 3.333X Input H L 6X Input Figure 2. NB3N511 Package Pinout, 8Pin (150 mil) SOIC (Top View) H M 3X Input H H 8X Input *Pins S1 and S0 default to M when open L = GND H = VDD M = OPEN (unconnected will default to VDD/2) Table 2. PIN DESCRIPTION Pin Name I/O Description 1 X1/ICLK Crystal or Crystal or external reference clock input LVCMOS/LVTTL Input 2 VDD Power supply Positive supply voltage 3 GND Power supply 0 V. Ground. 4 S1 Three level Input Multiplier select pin connect to V , GND or float DD 5 CLKOUT LVCMOS/LVTTL Clock output Output 6 S0 Three level Input Multiplier select pin connect to V , GND or float DD 7 OE LVCMOS/LVTTL Input Output Enable. CLKOUT is high impedance when OE is low. Internal pullup 8 X2 Crystal Crystal input Leave open when providing an external clock reference Table 3. COMMON OUTPUT FREQUENCY Table 4. COMMON OUTPUT FREQUENCY EXAMPLES EXAMPLES Output Frequency Input Frequency Output Frequency Input Frequency (MHz) (MHz) (MHz) (MHz) S1, S0 S1, S0 20 10 M, M 66.66 20 M, H 72 12 H, L 24 12 M, M 75 25 H, M 30 10 H, M 80 10 H, H 32 16 M, M 83.33 25 M, H 33.33 16.66 M, M 90 15 H, L 37.5 15 M, L 40 10 L, L 100 20 L, H 120 15 H, H 48 12 L, L 125 25 L, H 50 20 M, L 133.3 25 L, M 60 10 H, L 150 25 H, L 64 16 L, L www.onsemi.com 2