Ultrafast SiGe ECL Clock/Data Buffers Data Sheet ADCLK905/ADCLK907/ADCLK925 FEATURES TYPICAL APPLICATION CIRCUITS V REF V CC 95 ps propagation delay V T 7.5 GHz toggle rate 60 ps typical output rise/fall D Q 60 fs random jitter (RJ) D Q On-chip terminations at both input pins Extended industrial temperature range: 40C to +125C 2.5 V to 3.3 V power supply (V V ) CC EE V EE APPLICATIONS Figure 1. ADCLK905 ECL 1:1 Clock/Data Buffer Clock and data signal restoration and level shifting Automated test equipment (ATE) V 1 REF High speed instrumentation V 1 T High speed line receivers V CC Threshold detection D1 Q1 Converter clocking D1 Q1 V EE GENERAL DESCRIPTION The ADCLK905 (one input, one output), ADCLK907 (dual one V EE D2 Q2 input, one output), and ADCLK925 (one input, two outputs) are ultrafast clock/data buffers fabricated on the Analog Devices, Inc., D2 Q2 proprietary XFCB3 silicon germanium (SiGe) bipolar process. V CC V 2 T The ADCLK905/ADCLK907/ADCLK925 feature full-swing V 2 REF emitter coupled logic (ECL) output drivers. For PECL (positive Figure 2. ADCLK907 ECL Dual 1:1 Clock/Data Buffer ECL) operation, bias V to the positive supply and V to ground. CC EE For NECL (negative ECL) operation, bias VCC to ground and VEE to the negative supply. V REF V CC V T Q1 The buffers offer 95 ps propagation delay, 7.5 GHz toggle rate, 10 Gbps data rate, and 60 fs random jitter (RJ). Q1 D The inputs have center tapped, 100 , on-chip termination D Q2 resistors. A V pin is available for biasing ac-coupled inputs. REF Q2 The ECL output stages are designed to directly drive 800 mV V EE each side into 50 terminated to VCC 2 V for a total differential output swing of 1.6 V. Figure 3. ADCLK925 ECL 1:2 Clock/Data Fanout Buffer The ADCLK905/ADCLK907/ADCLK925 are available in 16-lead LFCSP packages. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20072017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 06318-001 06318-003 06318-002ADCLK905/ADCLK907/ADCLK925 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................9 Applications ....................................................................................... 1 Applications Information .............................................................. 12 General Description ......................................................................... 1 Power/Ground Layout and Bypassing ..................................... 12 Typical Application Circuits ............................................................ 1 Output Stages ............................................................................... 12 Revision History ............................................................................... 2 Optimizing High Speed Performance ..................................... 12 Specifications ..................................................................................... 3 Buffer Random Jitter .................................................................. 12 Electrical Characteristics ............................................................. 3 Typical Application Circuits ......................................................... 13 Absolute Maximum Ratings ............................................................ 5 Evaluation Board Schematic ......................................................... 14 Thermal Resistance ...................................................................... 5 Outline Dimensions ....................................................................... 15 ESD Caution .................................................................................. 5 Ordering Guide .......................................................................... 15 Pin Configurations and Function Descriptions ........................... 6 REVISION HISTORY 2/2017Rev. A to Rev. B Changes to Figure 4 and Table 4 ..................................................... 6 Changes to Figure 5 and Table 5 ..................................................... 7 Changes to Figure 6 and Table 6 ..................................................... 8 8/2016Rev. 0 to Rev. A Changed CP-16-3 to CP-16-27 .................................... Throughout Changes to Figure 4 and Table 4 ..................................................... 6 Changes to Figure 5 and Table 5 ..................................................... 7 Changes to Figure 6 and Table 6 ..................................................... 8 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 15 8/2007Revision 0: Initial Version Rev. B Page 2 of 16