Ultrafast, SiGe, Open-Collector HVDS Clock/Data Buffer Data Sheet ADCLK914 FEATURES FUNCTIONAL BLOCK DIAGRAM 7.5 GHz operating frequency 160 ps propagation delay V V CC REF 100 ps output rise/fall ADCLK914 V T 110 fs random jitter 50 50 50 50 On-chip input terminations Q D Extended industrial temperature range: 40C to +125C 3.3 V power supply (V V ) Q CC EE D APPLICATIONS Clock and data signal restoration V EE High speed converter clocking Broadband communications Figure 1. Cellular infrastructure High speed line receivers ATE and high performance instrumentation Level shifting Threshold detection The input has a center tapped, 100 , on-chip termination GENERAL DESCRIPTION resistor and accepts LVPECL, CML, CMOS, LVTTL, or LVDS The ADCLK914 is an ultrafast clock/data buffer fabricated on (ac-coupled only). A V pin is available for biasing ac-coupled REF the Analog Devices, Inc., proprietary, complementary bipolar inputs. (XFCB-3) silicon-germanium (SiGe) process. The ADCLK914 features high voltage differential signaling (HVDS) outputs The HVDS output stage is designed to directly drive 1.9 V each suitable for driving the latest Analog Devices high speed digital- side into 50 terminated to VCC for a total differential output to-analog converters (DACs). The ADCLK914 has a single, swing of 3.8 V. differential open-collector output. The ADCLK914 is available in a 16-lead LFCSP. It is specified for operation over the extended industrial temperature range of The ADCLK914 buffer operates up to 7.5 GHz with a 160 ps 40C to +125C. propagation delay and adds only 110 fs random jitter (RJ). Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20082017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 06561-001ADCLK914 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................7 Applications ....................................................................................... 1 Applications Information .................................................................9 Functional Block Diagram .............................................................. 1 Power/Ground Layout and Bypassing ........................................9 General Description ......................................................................... 1 HVDS Output Stage ......................................................................9 Table of Contents .............................................................................. 2 Interfacing to High Speed DACs .................................................9 Revision History ............................................................................... 2 Optimizing High Speed Performance ........................................9 Specif icat ions ..................................................................................... 3 Random Jitter .................................................................................9 Electrical Characteristics ............................................................. 3 Typical Application Circuits ..................................................... 10 Absolute Maximum Ratings ............................................................ 5 Outline Dimensions ....................................................................... 11 Thermal Performance .................................................................. 5 Ordering Guide .......................................................................... 11 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 REVISION HISTORY 9/2017Rev. A to Rev. B Updated Outline Dimensions ....................................................... 11 Changes to Ordering Guide .......................................................... 11 10/2008Rev. 0 to Rev. A Changes to Input Low Voltage Parameter, Table 1 ....................... 3 Changes to Output High Voltage Parameter, Table 1 ................ 3 Changes to Output Low Voltage Parameter, Table 1 .................. 3 Output Differential Range Parameter, Table 1 ............................ 3 Changes to Absolute Maximum Ratings Section ........................ 5 7/2008Revision 0: Initial Version Rev. B Page 2 of 11