Six LVPECL Outputs, SiGe Clock Fanout Buffer Data Sheet ADCLK946 FEATURES FUNCTIONAL BLOCK DIAGRAM 4.8 GHz operating frequency LVPECL ADCLK946 75 fs rms broadband random jitter Q0 On-chip input terminations Q0 V REFERENCE 3.3 V power supply REF Q1 Q1 V APPLICATIONS T Q2 CLK Low jitter clock distribution Q2 CLK Clock and data signal restoration Q3 Level translation Q3 Wireless communications Q4 Wired communications Q4 Medical and industrial imaging Q5 ATE and high performance instrumentation Q5 GENERAL DESCRIPTION Figure 1. The ADCLK946 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter. The device has a differential input equipped with center-tapped, differential, 100 on-chip termination resistors. The input accepts dc-coupled LVPECL, CML, 3.3 V CMOS (single ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREF pin is available for biasing ac-coupled inputs. The ADCLK946 features six full-swing emitter-coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias V to the positive supply and V to ground. For ECL CC EE operation, bias V to ground and V to the negative supply. CC EE The ECL output stages are designed to directly drive 800 mV each side into 50 terminated to V 2 V for a total differen- CC tial output swing of 1.6 V. The ADCLK946 is available in a 24-lead LFCSP and is specified for operation over the standard industrial temperature range of 40C to +85C. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20092017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 08053-001ADCLK946 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Performance ...................................................................5 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions ..............................6 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................7 Functional Block Diagram .............................................................. 1 Functional Description .....................................................................9 Revision History ............................................................................... 2 Clock Inputs ...................................................................................9 Specifications ..................................................................................... 3 Clock Outputs ................................................................................9 Electrical Characteristics ............................................................. 3 PCB Layout Considerations ...................................................... 10 Absolute Maximum Ratings ............................................................ 5 Input Termination Options ....................................................... 11 Determining Junction Temperature .......................................... 5 Outline Dimensions ....................................................................... 12 ESD Caution .................................................................................. 5 Ordering Guide .......................................................................... 12 REVISION HISTORY 8/2017Rev. A to Rev. B 5/2010Rev. 0 to Rev. A Changes to Figure 2 .......................................................................... 6 Changes to Table 1, DC Output Characteristics ........................... 3 Updated Outline Dimensions ....................................................... 12 Changes to Ordering Guide .......................................................... 12 4/2009Revision 0: Initial Version Rev. B Page 2 of 12