Single Channel, Configurable, Isolated Digital Input Data Sheet ADE1201 FEATURES GENERAL DESCRIPTION 1 Single channel, configurable, isolated digital input The ADE1201 is a single channel, configurable, isolated Programmable trip threshold digital input monitoring solution for energy transmission and On-chip debounce filter distribution applications. The ADE1201 is configured through On-chip data and power isolation the serial port interface (SPI) to perform an isolated measurement Application circuit monitors wide voltage range of the digital input that is also called binary input or contact 10 V dc to 300 V dc input. The ADE1201 digital output signal on the DOUT1 pin 8 V rms to 240 V rms ac reflects the state of the input signal after user configurable Programmable wetting current signal conditioning. The SPI protocol supports addressing to Pulse up to 205 mA allow up to eight devices sharing one 4-wire SPI port. Constant current up to 6.3 mA The ADE1201 application circuit accepts a wide range of input Safety and regulatory approvals voltages from 10 V dc to 300 V dc, or 8 V rms to 240 V rms. UL recognition The programmable wetting current and robust application 3750 V rms for 1 minute per UL 1577 circuit enable the device to meet stringent, system level CSA Component Acceptance Notice 5A (pending) electromagnetic capability (EMC) requirements. CSA 61010-1: 300 V rms The ADE1201 includes an isoPower integrated, isolated dc-to-dc VDE certificate of conformity (pending) converter that eliminates the need for an external isolated power DIN V VDE V 0884-11 (VDE V 0884-11):2017-1 supply. The iCoupler chip scale transformer technology is V = 565 V peak IORM used to isolate the logic signals between the high voltage, EMC robust solution supports relay protection system level isolated side and the low voltage, nonisolated side of the requirements digital input monitor. This technology creates a small form ADC samples available for system diagnostics factor design that includes data and power isolation. Internal SAR ADC with PGA Single 3.3 V supply An integrated successive approximation register (SAR) Integrated isoPower, isolated dc-to-dc converter analog-to-digital converter (ADC) and a programmable gain Interfaces amplifier (PGA) from 1 to 10 measure the analog inputs. SPI The ADC waveforms are available through the SPI port to DOUT1 output reflects state of digital input allow system level diagnostics. IRQ interrupt pin PRODUCT HIGHLIGHTS Operating temperature: 40C to +125C 20-lead, LGA package with 6.8 mm creepage 1. Single channel, configurable, isolated digital input. 2. Single hardware design supports 24 V to 300 V systems. APPLICATIONS 3. Robust architecture. Energy transmission and distribution 4. Enables system level diagnostics. Multifunction relay protection Substation battery monitoring Bay or substation interlocking Merge unit Circuit breaker status indication Remote terminal unit Building automation 1 Protected by U.S. Patent Number 2017/0250043. Other patents pending. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. ADE1201 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Decoupling and Ground Plane Connection ........................... 28 Applications ....................................................................................... 1 Electomagnetic Interface (EMI) Capacitor ............................. 28 General Description ......................................................................... 1 Applications Information .............................................................. 29 Product Highlights ........................................................................... 1 Register Map ................................................................................... 30 Revision History ............................................................................... 2 Register Details ............................................................................... 31 Functional Block Diagram .............................................................. 3 Lock Register ............................................................................... 31 Specif icat ions ..................................................................................... 4 Control Register ......................................................................... 31 Electrical Characteristics ............................................................. 4 Binary Channel Control Register ............................................. 32 Timing Characteristics ................................................................ 6 Binary Channel Threshold Level Register .............................. 33 Insulation and Safety Related Specifications ............................ 7 WARNA1 Channel Threshold Level Register ........................ 33 Package Characteristics ............................................................... 7 WARNB1 Channel Threshold Level Register ......................... 33 Regulatory Information ............................................................... 8 WARNC1 Channel Threshold Level Register ........................ 33 DIN V VDE V 0884-11 (VDE V 0884-11) Insulation Binary Channel Configuration Register ................................. 34 Characteristics .............................................................................. 9 WARNA1 Datapath Configuration Register .......................... 34 Absolute Maximum Ratings .......................................................... 10 WARNB1 Datapath Configuration Register .......................... 34 Thermal Resistance .................................................................... 10 WARNC1 Datapath Configuration Register .......................... 34 ESD Caution ................................................................................ 10 Interrupt Mask Register ............................................................. 35 Pin Configuration and Function Descriptions ........................... 11 Interrupt Status Register ............................................................ 35 Typical Performance Characteristics ........................................... 12 Status Register ............................................................................. 36 Test Circuit ...................................................................................... 15 ADC Register .............................................................................. 36 Theory of Operation ...................................................................... 16 ADC Decimated Register .......................................................... 36 Power Supply and Conditioning .............................................. 16 Programmable Load Control Register .................................... 37 Digital Inputs Signal Path .......................................................... 17 Programmable Load Rise Threshold Register ........................ 37 Invalid Mode ............................................................................... 20 Programmable Load Low Code Register ................................ 37 Programmable Load Current .................................................... 20 Programmable Load High Code Register ............................... 37 External FET Protection ............................................................ 22 Programmable Load High Current Period Register .............. 38 Gate Drive .................................................................................... 23 Energy Meter Control Register ................................................ 38 Thermal Shutdown ..................................................................... 24 Energy Meter Maximum Threshold Register ......................... 38 Inter r upt ....................................................................................... 24 Energy Meter Channel 1 Accumulator Register .................... 38 SPI Protocol Overview ............................................................... 24 Programmable Load Enable Register ...................................... 39 Protecting the Integrity of Configuration Registers .............. 26 PGA Gain Register ..................................................................... 39 Version ......................................................................................... 27 Outline Dimensions ....................................................................... 40 Insulation Wear Out ................................................................... 27 Ordering Guide .......................................................................... 40 Layout Guidelines ........................................................................... 28 Ferrite Bead ................................................................................. 28 REVISION HISTORY 12/2019Revision 0: Initial Version Rev. 0 Page 2 of 40