Phase Detector/Frequency Synthesizer Data Sheet ADF4002 FEATURES GENERAL DESCRIPTION 400 MHz bandwidth The ADF4002 frequency synthesizer is used to implement local 2.7 V to 3.3 V power supply oscillators in the upconversion and downconversion sections of Separate charge pump supply (V ) allows extended P wireless receivers and transmitters. It consists of a low noise tuning voltage in 3 V systems digital phase frequency detector (PFD), a precision charge Programmable charge pump currents pump, a programmable reference divider, and programmable 3-wire serial interface N divider. The 14-bit reference counter (R counter) allows Analog and digital lock detect selectable REFIN frequencies at the PFD input. A complete Hardware and software power-down mode phase-locked loop (PLL) can be implemented if the synthesizer 104 MHz phase detector is used with an external loop filter and voltage controlled oscillator (VCO). In addition, by programming R and N to 1, APPLICATIONS the device can be used as a standalone PFD and charge pump. Clock conditioning Clock generation IF LO generation FUNCTIONAL BLOCK DIAGRAM AV DV R V CPGND DD DD P SET REFERENCE 14-BIT PHASE REF CHARGE IN R COUNTER FREQUENCY CP PUMP DETECTOR 14 R COUNTER LOCK CURRENT CURRENT LATCH DETECT SETTING 2 SETTING 1 CLK FUNCTION 24-BIT INPUT CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 DATA REGISTER LATCH 22 LE HIGH Z N COUNTER LATCH SD OUT AV DD MUXOUT MUX SD OUT RF A 13-BIT IN RF B N COUNTER IN M3 M2 M1 ADF4002 CE AGND DGND Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com 06052-001ADF4002 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 MUXOUT and Lock Detect .........................................................9 Applications ....................................................................................... 1 Input Shift Register .......................................................................9 General Description ......................................................................... 1 Latch Maps and Descriptions ....................................................... 10 Functional Block Diagram .............................................................. 1 Latch Summary ........................................................................... 10 Revision History ............................................................................... 2 Reference Counter Latch Map .................................................. 11 Specif icat ions ..................................................................................... 3 N Counter Latch Map ................................................................ 12 Timing Characteristics ................................................................ 4 Function Latch Map ................................................................... 13 Absolute Maximum Ratings ............................................................ 5 Initialization Latch Map ............................................................ 14 Thermal Characteristics .............................................................. 5 Function Latch ............................................................................ 15 ESD Caution .................................................................................. 5 Initialization Latch ..................................................................... 16 Pin Configurations and Function Descriptions ........................... 6 Applicat ions ..................................................................................... 17 Typical Performance Characteristics ............................................. 7 Very Low Jitter Encode Clock for High Speed Converters ... 17 Theory of Operation ........................................................................ 8 PFD............................................................................................... 17 Reference Input Section ............................................................... 8 Interfacing ................................................................................... 17 RF Input Stage ............................................................................... 8 PCB Design Guidelines for Chip Scale Package .................... 18 N Counter ...................................................................................... 8 Outline Dimensions ....................................................................... 19 R Counter ...................................................................................... 8 Ordering Guide .......................................................................... 19 Phase Frequency Detector (PFD) and Charge Pump .............. 8 REVISION HISTORY 9/15Rev. C to Rev. D 9/11Rev. A to Rev. B Changed ADSP21xx to ADSP-2181 ............................ Throughout Changes to Normalized Phase Noise Floor (PNSYNTH) Parameter Changes to Table 3 ............................................................................ 5 and Endnote 6, Table 1 ..................................................................... 4 Changes to Figure 4 .......................................................................... 6 Added Normalized 1/f Noise (PN ) Parameter and Endnote 7, 1 f Changes to Very Low Jitter Encode Clock for High Speed Table 1 ................................................................................................. 4 Converters Section and Figure 20 ................................................ 17 Changes to Figure 4 and Table 5 ...................................................... 6 Update Outline Dimensions ......................................................... 19 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 19 4/07Rev. 0 to Rev. A 12/12Rev. B to Rev. C Changes to Features List ................................................................... 1 Change to Table 1 ............................................................................. 4 Changes to Table 1 ............................................................................. 3 Added RF A to RF B Parameter, Table 3 .................................... 5 Deleted Figure .................................................................................... 7 IN IN Updated Outline Dimensions ....................................................... 19 Changes to Figure 16 ...................................................................... 11 Changes to Ordering Guide .......................................................... 19 4/06Revision 0: Initial Version Rev. D Page 2 of 20