18 GHz Microwave PLL Synthesizer Data Sheet ADF41020 FEATURES GENERAL DESCRIPTION 18 GHz maximum RF input frequency The ADF41020 frequency synthesizer can be used to implement Integrated SiGe prescaler local oscillators as high as 18 GHz in the up conversion and Software compatible with the ADF4106/ADF4107/ADF4108 down conversion sections of wireless receivers and transmitters. family of PLLs It consists of a low noise, digital phase frequency detector 2.85 V to 3.15 V PLL power supply (PFD), a precision charge pump, a programmable reference Programmable dual-modulus prescaler divider, and high frequency programmable feedback dividers 8/9, 16/17, 32/33, 64/65 (A, B, and P). A complete phase-locked loop (PLL) can be Programmable charge pump currents implemented if the synthesizer is used with an external loop 3-wire serial interface filter and voltage controlled oscillator (VCO). The synthesizer Digital lock detect can be used to drive external microwave VCOs via an active Hardware and software power-down mode loop filter. Its very high bandwidth means a frequency doubler 4000 V HBM/1500 V CDM ESD performance stage can be eliminated, simplifying system architecture and reducing cost. The ADF41020 is software-compatible with the APPLICATIONS existing ADF4106/ADF4107/ADF4108 family of devices from Microwave point-to-point/multipoint radios Analog Devices, Inc. Their pinouts match very closely with Wireless infrastructure the exception of the ADF41020s single-ended RF input pin, VSAT radios meaning only a minor layout change is required when updating Test equipment current designs. Instrumentation FUNCTIONAL BLOCK DIAGRAM AV DV V R DD DD P GND SET REFERENCE PHASE REF R COUNTER IN CHARGE FREQUENCY CP PUMP DETECTOR R COUNTER LOCK CURRENT CURRENT LATCH DETECT SETTING 1 SETTING 2 CLK 24-BIT INPUT FUNCTION CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 DATA REGISTER LATCH LE HIGH-Z A, B COUNTER LATCH AV DD MUXOUT MUX N = 4(BP + A) SD OUT 3pF DIVIDE A AND B RF IN P/P+ 1 COUNTERS BY 4 M3 M2 M1 50 ADF41020 GND CE GND Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20122014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com 10304-001ADF41020 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 RF Input Stage ................................................................................8 Applications ....................................................................................... 1 Pres caler ..........................................................................................8 General Description ......................................................................... 1 A Counter and B Counter ............................................................8 Functional Block Diagram .............................................................. 1 R Counter .......................................................................................9 Revision History ............................................................................... 2 PFD and Charge Pump .................................................................9 Specif icat ions ..................................................................................... 3 MUXOUT and Lock Detect .........................................................9 Timing Characteristics ................................................................ 4 Input Shift Register .......................................................................9 Absolute Maximum Ratings ............................................................ 5 The Function Latch .................................................................... 13 ESD Caution .................................................................................. 5 Applications Information .............................................................. 15 Pin Configuration and Function Descriptions ............................. 6 Interfacing ................................................................................... 15 Typical Performance Characteristics ............................................. 7 PCB Design Guidelines ............................................................. 15 Theory of Operation ........................................................................ 8 Outline Dimensions ....................................................................... 16 Reference Input Section ............................................................... 8 Ordering Guide .......................................................................... 16 REVISION HISTORY 12/14Rev. B to Rev. C Changes to Features Section............................................................ 1 Changes to Lock Detect Section ..................................................... 9 1/14Rev. A to Rev. B Changes to Figure 6 .......................................................................... 7 11/13Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Changes to Absolute Maximum Ratings Section and Table 3 .... 5 10/12Revision 0: Initial Version Rev. C Page 2 of 16