PLL Frequency Synthesizer Data Sheet ADF4106 FEATURES GENERAL DESCRIPTION 6.0 GHz bandwidth The ADF4106 frequency synthesizer can be used to implement 2.7 V to 3.3 V power supply local oscillators in the up-conversion and down-conversion Separate charge pump supply (V ) allows extended P sections of wireless receivers and transmitters. It consists of a tuning voltage in 3 V systems low noise, digital phase frequency detector (PFD), a precision Programmable dual-modulus prescaler charge pump, a programmable reference divider, programmable 8/9, 16/17, 32/33, 64/65 A counter and B counter, and a dual-modulus prescaler (P/P + 1). Programmable charge pump currents The A (6-bit) counter and B (13-bit) counter, in conjunction Programmable antibacklash pulse width with the dual-modulus prescaler (P/P + 1), implement an N 3-wire serial interface divider (N = BP + A). In addition, the 14-bit reference counter Analog and digital lock detect (R Counter) allows selectable REFIN frequencies at the PFD Hardware and software power-down mode input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage APPLICATIONS controlled oscillator (VCO). Its very high bandwidth means that frequency doublers can be eliminated in many high Broadband wireless access frequency systems, simplifying system architecture and Satellite systems reducing cost. Instrumentation Wireless LANS Base stations for wireless radios FUNCTIONAL BLOCK DIAGRAM AV DV V R CPGND DD DD P SET REFERENCE 14-BIT PHASE REF IN CHARGE R COUNTER CP FREQUENCY PUMP DETECTOR 14 R COUNTER LOCK CURRENT CURRENT LATCH DETECT SETTING 1 SETTING 2 CLK 24-BIT INPUT FUNCTION CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 DATA REGISTER LATCH 22 LE HIGH Z A, B COUNTER FROM LATCH SD OUT 19 AV FUNCTION DD MUXOUT LATCH MUX 13 N = BP + A 13-BIT SD OUT B COUNTER LOAD RF A PRESCALER IN P/P + 1 RF B IN LOAD M3 M2 M1 6-BIT A COUNTER ADF4106 6 CE AGND DGND Figure 1. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20012015 Analog Devices, Inc. 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Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 02720-001ADF4106 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 A Counter and B Counter ......................................................... 10 Applications ....................................................................................... 1 R Counter .................................................................................... 10 General Description ......................................................................... 1 Phase Frequency Detector (PFD) and Charge Pump ............ 11 Functional Block Diagram .............................................................. 1 MUXOUT and Lock Detect ...................................................... 11 Revision History ............................................................................... 2 Input Shift Register .................................................................... 11 Specifications ..................................................................................... 3 The Function Latch .................................................................... 17 Timing Characterisitics ............................................................... 4 The Initialization Latch ............................................................. 18 Absolute Maximum Ratings ............................................................ 6 Applications ..................................................................................... 19 ESD Caution .................................................................................. 6 Local Oscillator for LMDS Base Station Transmitter ............ 19 Pin Configurations and Function Descriptions ........................... 7 Interfacing ................................................................................... 20 Typical Performance Characteristics ............................................. 8 PCB Design Guidelines for Chip Scale Package .................... 20 General Description ....................................................................... 10 Outline Dimensions ....................................................................... 21 Reference Input Section ............................................................. 10 Ordering Guide .......................................................................... 22 RF Input Stage ............................................................................. 10 Prescaler (P/P +1) ....................................................................... 10 REVISION HISTORY 4/15Rev. E to Rev. F 6/05Rev. A to Rev. B Change to RF A to RF B Parameter, Table 3 .............................. 6 Updated Format .................................................................. Universal IN IN Updated Outline Dimensions ....................................................... 21 Changes to Figure 1 ........................................................................... 1 Changes to Ordering Guide .......................................................... 22 Changes to Table 1 ............................................................................. 3 Changes to Table 2 ............................................................................. 4 11/12Rev. D to Rev. E Changes to Table 3 ............................................................................. 5 Changed EVAL-ADF4106EBZ1 to EV-ADF4106SD1Z ...... Universal Changes to Figure 3 and Figure 4 .................................................... 6 Added RF A to RF B Parameter, Table 3 .................................... 6 IN IN Changes to Figure 6 ........................................................................... 7 Updated Outline Dimensions ....................................................... 21 Changes to Figure 10 ......................................................................... 7 Changes to Ordering Guide .......................................................... 22 Deleted TPC 13 and TPC 14 ............................................................ 8 Changes to Figure 15 ......................................................................... 8 9/11Rev. C to Rev. D Changes to Figure 20 Caption ...................................................... 10 Changes to Normalized Phase Noise Floor (PNSYNTH) Parameter, Updated Outline Dimensions ....................................................... 20 Table 1 ................................................................................................ 4 Changes to Ordering Guide .......................................................... 21 Added Normalized 1/f Noise (PN1 f) Parameter and Endnote 12, Table 1 ................................................................................................ 4 5/03Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 22 Edits to Specifications ....................................................................... 2 Edits to TPC 11 ..................................................................................7 2/10Rev. B to Rev. C Updated Outline Dimensions ....................................................... 19 Changes to Figure 4 and Table 4 ..................................................... 6 Changes to Figure 12 ........................................................................ 8 10/01Revision 0: Initial Revision Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 21 Rev. F Page 2 of 24