PLL Frequency Synthesizer Enhanced Product ADF4106-EP FEATURES GENERAL DESCRIPTION 6.0 GHz bandwidth The ADF4106-EP frequency synthesizer can be used to 2.7 V to 3.3 V power supply implement local oscillators in the up-conversion and down- Separate charge pump supply (V ) allows extended tuning P conversion sections of wireless receivers and transmitters. It voltage in 3 V systems consists of a low noise, digital phase frequency detector (PFD), Programmable dual-modulus prescaler a precision charge pump, a programmable reference divider, 8/9, 16/17, 32/33, 64/65 programmable A counter and B counter, and a dual-modulus Programmable charge pump currents prescaler (P/P + 1). The A (6-bit) counter and B (13-bit) counter, in Programmable antibacklash pulse width conjunction with the dual-modulus prescaler (P/P + 1), implement 3-wire serial interface an N divider (N = BP + A). In addition, the 14-bit reference Analog and digital lock detect counter (R counter) allows selectable REFIN frequencies at the Hardware and software power-down mode PFD input. A complete phase-locked loop (PLL) can be Support defense and aerospace applications (AQEC) implemented if the synthesizer is used with an external loop Military temperature range (55C to +125C) filter and voltage controlled oscillator (VCO). Its very high Controlled manufacturing baseline bandwidth means that frequency doublers can be eliminated in One assembly/test site many high frequency systems, simplifying system architecture One fabrication site and reducing cost. Product change notification Qualification data available upon request Additional application and technical information can be found in the ADF4106 data sheet. APPLICATIONS Broadband wireless access Satellite systems Instrumentation Wireless LANS Base stations for wireless radios FUNCTIONAL BLOCK DIAGRAM AV DV V CPGND R DD DD SET P REFERENCE 14-BIT PHASE REF IN CHARGE R COUNTER CP FREQUENCY PUMP DETECTOR 14 R COUNTER LOCK CURRENT CURRENT LATCH DETECT SETTING 1 SETTING 2 CLK 24-BIT INPUT FUNCTION CPI6 CPI5 CPI4 DATA CPI3 CPI2 CPI1 REGISTER LATCH 22 LE HIGH Z A, B COUNTER FROM LATCH SD OUT 19 FUNCTION AV DD MUXOUT LATCH MUX 13 N = BP + A 13-BIT SD OUT B COUNTER LOAD RF A IN PRESCALER RF B P/P + 1 IN LOAD M3 M2 M1 6-BIT A COUNTER ADF4106-EP 6 CE AGND DGND Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20102018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 09272-001ADF4106-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................5 Applications ....................................................................................... 1 Pin Configurations and Function Descriptions ............................6 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................7 Functional Block Diagram .............................................................. 1 Printed Circuit Board (PCB) Design Guidelines for Chip Scale Package ................................................................................................9 Revision History ............................................................................... 2 Outline Dimensions ....................................................................... 10 Specifications ..................................................................................... 3 Ordering Guide .......................................................................... 10 Timing Characterisitics ............................................................... 4 Absolute Maximum Ratings ............................................................ 5 REVISION HISTORY 10/2018Rev. C to Rev. D 11/2010Rev. 0 to Rev. A Change to Features Section ............................................................. 1 Changes to Figure 6 ........................................................................... 7 Changes to Figure 6 .......................................................................... 7 Changes to Figure 11 ......................................................................... 8 Changes to Ordering Guide .......................................................... 10 Changes to Ordering Guide .......................................................... 10 11/2014Rev. B to Rev. C 8/2010Revision 0: Initial Version Change to Table 1 ............................................................................. 3 Change to Table 2 ............................................................................. 4 Changes to Table 3 ............................................................................ 5 8/2012Rev. A to Rev. B Changes to Table 3 ............................................................................ 5 Updated Outline Dimensions ....................................................... 10 Changes to Ordering Guide .......................................................... 10 Rev. D Page 2 of 10