PLL Frequency Synthesizer Data Sheet ADF4107 FEATURES GENERAL DESCRIPTION 7.0 GHz bandwidth The ADF4107 frequency synthesizer can be used to implement 2.7 V to 3.3 V power supply local oscillators in the upconversion and downconversion sections Separate charge pump supply (V ) allows extended tuning P of wireless receivers and transmitters. It consists of a low noise voltage in 3 V systems digital PFD (phase frequency detector), a precision charge pump, a Programmable dual-modulus prescaler programmable reference divider, programmable A and B counters, 8/9, 16/17, 32/33, 64/65 and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B Programmable charge pump currents (13-bit) counters, in conjunction with the dual-modulus Programmable antibacklash pulse width prescaler (P/P + 1), implement an N divider (N = BP + A). In 3-wire serial interface addition, the 14-bit reference counter (R counter), allows Analog and digital lock detect selectable REFIN frequencies at the PFD input. A complete PLL Hardware and software power-down mode (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled APPLICATIONS oscillator). Its very high bandwidth means that frequency Broadband wireless access doublers can be eliminated in many high frequency systems, Satellite systems simplifying system architecture and reducing cost. Instrumentation Wireless LANs Base stations for wireless radio FUNCTIONAL BLOCK DIAGRAM AV DV V R DD DD CPGND SET P REFERENCE 14-BIT PHASE REF IN CHARGE R COUNTER CP FREQUENCY PUMP DETECTOR 14 R COUNTER LOCK CURRENT CURRENT LATCH DETECT SETTING 1 SETTING 2 CLK 24-BIT INPUT FUNCTION CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 DATA REGISTER LATCH 22 LE HIGH Z A, B COUNTER FROM LATCH SD 19 OUT AV FUNCTION DD MUXOUT LATCH MUX 13 N = BP + A 13-BIT SD OUT B COUNTER LOAD RF A PRESCALER IN RF B P/P + 1 IN LOAD M3 M2 M1 6-BIT A COUNTER ADF4107 6 CE AGND DGND Figure 1. Rev. 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Technical Support www.analog.com 03338-001ADF4107 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Phase Frequency Detector and Charge Pump ..............................9 Applications ....................................................................................... 1 MUXOUT and Lock Detect ...................................................... 10 General Description ......................................................................... 1 Input Shift Register .................................................................... 10 Functional Block Diagram .............................................................. 1 Latch Summary........................................................................... 11 Revision History ............................................................................... 2 Reference Counter Latch Map .................................................. 12 Specifications ..................................................................................... 3 AB Counter Latch Map ............................................................. 13 Timing Characteristics ................................................................ 4 Function Latch Map ................................................................... 14 Absolute Maximum Ratings ............................................................ 5 Initialization Latch Map ............................................................ 15 ESD Caution .................................................................................. 5 Function Latch ............................................................................ 16 Pin Configurations and Function Descriptions ........................... 6 Initialization Latch ..................................................................... 17 Typical Performance Characteristics ............................................. 7 Device Programming after Initial Power-Up ............................. 17 Functional Description .................................................................... 9 Applications ..................................................................................... 18 Reference Input Stage ................................................................... 9 Local Oscillator for LMDS Base Station Transmitter ............ 18 RF Input Stage ............................................................................... 9 Interfacing ................................................................................... 19 Prescaler (P/P + 1) ........................................................................ 9 PCB Design Guidelines for Chip Scale Package .................... 19 A and B Counters ......................................................................... 9 Outline Dimensions ....................................................................... 20 R Counter ...................................................................................... 9 Ordering Guide .......................................................................... 20 REVISION HISTORY 3/13Rev. C to Rev. D 4/07Rev. 0 to Rev. A Changed RFINA to RFINB Parameter from 320 mV to 600 mV, Updated Format .................................................................. Universal Table 3 ................................................................................................ 5 Changes to REFIN Characteristics Section ................................... 3 Updated Outline Dimensions ....................................................... 20 Changes to Noise Characteristics Section ...................................... 4 Changes to Ordering Guide .......................................................... 20 Changes to Absolute Maximum Ratings Section .......................... 5 Changes to Figure 23 ...................................................................... 12 11/12Rev. B to Rev. C Changes to Ordering Guide .......................................................... 20 Changed EVAL-ADF411xEBZ1 to EV-ADF411XSD1Z ............. 4 Changes to Table 3 ............................................................................ 5 5/03Revision 0: Initial Version Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 20 9/11Rev. A to Rev. B Changes to Normalized Phase Noise Floor (PNSYNTH) Parameter, Table 1 ................................................................................................ 3 Added Normalized 1/f Noise (PN1 f) Parameter and Endnote 11, Table 1 ................................................................................................ 3 Changed EVAL-ADF4107EB1 to EVAL-ADF411xEBZ1 ............ 4 Changes to Figure 4 and Table 4 ..................................................... 6 Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 20 Rev. D Page 2 of 20