PLL Frequency Synthesizer Data Sheet ADF4108 FEATURES GENERAL DESCRIPTION 8.0 GHz bandwidth The ADF4108 frequency synthesizer can be used to implement 3.2 V to 3.6 V power supply local oscillators in the upconversion and downconversion sections Separate charge pump supply (V ) allows extended tuning P of wireless receivers and transmitters. It consists of a low noise voltage in 3.3 V systems digital PFD (phase frequency detector), a precision charge pump, a Programmable, dual-modulus prescaler programmable reference divider, programmable A and B counters, 8/9, 16/17, 32/33, or 64/65 and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B Programmable charge pump currents (13-bit) counters, in conjunction with the dual-modulus prescaler Programmable antibacklash pulse width (P/P + 1), implement an N divider (N = BP + A). In addition, 3-wire serial interface the 14-bit reference counter (R counter), allows selectable REF IN Analog and digital lock detect frequencies at the PFD input. A complete phase-locked loop (PLL) Hardware and software power-down mode can be implemented if the synthesizer is used with an external Loop filter design possible with ADIsimPLL loop filter and voltage controlled oscillator (VCO). Its very high 4 mm 4 mm, 20-lead chip scale package bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture APPLICATIONS and reducing cost. Broadband wireless access Satellite systems Instrumentation Wireless LANs Base stations for wireless radio FUNCTIONAL BLOCK DIAGRAM AV DV R V CPGND DD DD P SET REFERENCE 14-BIT PHASE REF IN CHARGE R COUNTER FREQUENCY CP PUMP DETECTOR 14 R COUNTER LOCK CURRENT CURRENT LATCH DETECT SETTING 2 SETTING 1 CLK 24-BIT INPUT FUNCTION CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 DATA REGISTER LATCH 22 LE HIGH-Z A, B COUNTER FROM LATCH SD OUT 19 FUNCTION AV DD MUXOUT LATCH MUX 13 N = BP + A 13-BIT SD OUT B COUNTER LOAD RF A IN PRESCALER P/P + 1 RF B IN LOAD M3 M2 M1 6-BIT A COUNTER ADF4108 6 CE AGND DGND Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com 06015-001ADF4108 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Phase Frequency Detector and Charge Pump ........................ 10 Applications ....................................................................................... 1 MUXOUT and Lock Detect ...................................................... 10 General Description ......................................................................... 1 Input Shift Register .................................................................... 10 Functional Block Diagram .............................................................. 1 Latch Summary ........................................................................... 11 Revision History ............................................................................... 2 Reference Counter Latch Map .................................................. 12 Specif icat ions ..................................................................................... 3 AB Counter Latch Map ............................................................. 13 Timing Characteristics ................................................................ 5 Function Latch Map ................................................................... 14 Absolute Maximum Ratings ............................................................ 6 Initialization Latch Map ............................................................ 15 ESD Caution .................................................................................. 6 Function Latch ............................................................................ 16 Pin Configuration and Function Descriptions ............................. 7 Initialization Latch ..................................................................... 17 Typical Performance Characteristics ............................................. 8 Power Supply Considerations ................................................... 17 Theory of Operation ........................................................................ 9 Interfacing ....................................................................................... 18 Reference Input Stage ................................................................... 9 ADuC812 Interface .................................................................... 18 RF Input Stage ............................................................................... 9 ADSP-21xx Interface ................................................................. 18 Prescaler (P/P + 1) ........................................................................ 9 PCB Design Guidelines for Chip Scale Package ......................... 19 A and B Counters ......................................................................... 9 Outline Dimensions ....................................................................... 20 R Counter ...................................................................................... 9 Ordering Guide .......................................................................... 20 REVISION HISTORY 4/13Rev. D to Rev. E 12/07Rev. 0 to Rev. A Changed RFINA to RFINB Parameter from 320 mV to 600 mV, Removed TSSOP Package ................................................. Universal Table 3 ................................................................................................ 6 Changes to Features .......................................................................... 1 1/13Rev. C to Rev. D Changes to Table 1 Endnote 10 and Endnote 11 ........................... 4 Changes to Table 3 ............................................................................. 6 Change to Table 1 .................................................................................... 4 Deleted Figure 3 ................................................................................. 7 Added RF A to RF B Parameter, Table 4 ..................................... 6 IN IN Changes to Table 4 ............................................................................. 7 7/12Rev. B to Rev. C Changes to Figure 10 and Figure 11................................................ 8 Changes to Figure 3 .......................................................................... 7 Updated Outline Dimensions ....................................................... 20 Updated Outline Dimensions (Changed CP-20-1 to CP-20-6) ...... 20 Deleted Figure 24 ............................................................................ 20 Changes to Ordering Guide .......................................................... 20 Changes to Ordering Guide .......................................................... 20 9/11Rev. A to Rev. B 4/06Revision 0: Initial Version Changes to Normalized Phase Noise Floor (PN ) Parameter SYNTH and Endnote 9, Table 1 ..................................................................... 4 Added Normalized 1/f Noise (PN1 f) Parameter and Endnote 10, Table 1 ................................................................................................ 4 Changes to Figure 3 and Table 4 ..................................................... 7 Updated Outline Dimensions ....................................................... 20 Rev. E Page 2 of 20