Fractional-N/Integer-N PLL Synthesizer Data Sheet ADF4150 FEATURES GENERAL DESCRIPTION Fractional-N synthesizer and integer-N synthesizer The ADF4150 allows implementation of fractional-N or Programmable divide-by-1/-2/-4/-8/-16 output integer-N phase-locked loop (PLL) frequency synthesizers 5.0 GHz RF bandwidth if used with an external voltage-controlled oscillator (VCO), 3.0 V to 3.6 V power supply loop filter, and external reference frequency. 1.8 V logic compatibility The ADF4150 is for use with external VCO parts and is Separate charge pump supply (V ) allows extended tuning P software compatible with the ADF4350. The VCO frequency voltage in 3 V systems can be divided by 1/2/4/8/16 to allow the user to generate RF Programmable dual-modulus prescaler of 4/5 or 8/9 output frequencies as low as 31.25 MHz. For applications that Programmable output power level require isolation the RF output stage can be muted. The mute RF output mute function function is both pin and software controllable. 3-wire serial interface Control of all the on-chip registers is through a simple 3-wire Analog and digital lock detect interface. The device operates with a power supply ranging Switched bandwidth fast-lock mode from 3.0 V to 3.6 V and can be powered down when not in use. Cycle slip reduction The ADF4150 is available in a 4 mm 4 mm package. APPLICATIONS Wireless infrastructure (W-CDMA, TD-SCDMA, WiMax, GSM, PCS, DCS, DECT) Test equipment Wireless LANs, CATV equipment Clock generation FUNCTIONAL BLOCK DIAGRAM SDV AV DV V R DD DD DD P SET MULTIPLEXER MUXOUT 10-BIT R 2 2 COUNTER DIVIDER REF IN DOUBLER LOCK DETECT SW FL SWITCH O LD CLK DATA DATA REGISTER FUNCTION CHARGE CP LATCH OUT LE PUMP PHASE COMPARATOR RF + OUT OUTPUT DIVIDE-BY-1/ INTEGER FRACTION MODULUS STAGE -2/-4/-8/-16 RF REG REG REG OUT PDB RF THIRD-ORDER FRACTIONAL RF + RF IN INTERPOLATOR MULTIPLEXER INPUT RF IN N COUNTER ADF4150 CE A CP SD GND GND GND Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com 08226-001ADF4150 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register 1 ..................................................................................... 18 Applications ....................................................................................... 1 Register 2 ..................................................................................... 18 General Description ......................................................................... 1 Register 3 ..................................................................................... 20 Functional Block Diagram .............................................................. 1 Register 4 ..................................................................................... 20 Revision History ............................................................................... 2 Register 5 ..................................................................................... 20 Specifications ..................................................................................... 3 Initialization Sequence .............................................................. 20 Timing Characteristics ................................................................ 5 RF SynthesizerA Worked Example ...................................... 21 Absolute Maximum Ratings ............................................................ 6 Modulus ....................................................................................... 21 Transistor Count ........................................................................... 6 Reference Doubler and Reference Divider ............................. 21 ESD Caution .................................................................................. 6 12-Bit Programmable Modulus ................................................ 21 Pin Configuration and Function Descriptions ............................. 7 Cycle Slip Reduction for Faster Lock Times ........................... 22 Typical Performance Characteristics ............................................. 9 Spurious Optimization and Fast lock ...................................... 22 Circuit Description ......................................................................... 11 Fast Lock Timer and Register Sequences ................................ 22 Reference Input Section ............................................................. 11 Fast LockAn Example ............................................................ 23 RF N Divider ............................................................................... 11 Fast LockLoop Filter Topology............................................. 23 INT, FRAC, MOD, and R Counter Relationship.................... 11 Spur Mechanisms ....................................................................... 23 INT N Mode ................................................................................ 11 Spur Consistency and Fractional Spur Optimization ........... 24 R Counter .................................................................................... 11 Phase Resync ............................................................................... 24 Phase Frequency Detector (PFD) and Charge Pump ............ 11 Applications Information .............................................................. 25 MUXOUT and Lock Detect ...................................................... 12 Direct Conversion Modulator .................................................. 25 Input Shift Registers ................................................................... 12 Interfacing ................................................................................... 26 Program Modes .......................................................................... 12 PCB Design Guidelines for Chip Scale Package .................... 26 Output Stage ................................................................................ 12 Output Matching ........................................................................ 27 Register Maps .................................................................................. 13 Outline Dimensions ....................................................................... 28 Register 0 ..................................................................................... 18 Ordering Guide .......................................................................... 28 REVISION HISTORY 11/13Rev. 0 to Rev. A Changes to Pin 24, Table 4................................................................ 8 7/11Revision 0: Initial Version Rev. A Page 2 of 28