High Voltage, Fractional-N/ Integer-N PLL Synthesizer ADF4150HV FEATURES GENERAL DESCRIPTION Fractional-N synthesizer and integer-N synthesizer The ADF4150HV is a 3.0 GHz, fractional-N or integer-N High voltage charge pump: V = 6 V to 30 V P frequency synthesizer with an integrated high voltage charge Tuning range: 1.0 V to 29 V (or 1 V from V supply rails) P pump. The synthesizer can be used to drive external wideband RF bandwidth to 3.0 GHz VCOs directly, eliminating the need for operational amplifiers Programmable divide-by-1/-2/-4/-8/-16 outputs to achieve higher tuning voltages. This simplifies design and Synthesizer power supply: 3.0 V to 3.6 V reduces cost while improving phase noise, in contrast to active Programmable dual-modulus prescaler of 4/5 or 8/9 filter topologies, which tend to degrade phase noise compared Programmable output power level to passive filter topologies. Programmable charge pump currents The VCO frequency can be divided by 1, 2, 4, 8, or 16 to allow RF output mute function the user to generate RF output frequencies as low as 31.25 MHz. 3-wire serial interface For applications that require isolation, the RF output stage can be Analog and digital lock detect muted. The mute function is both pin- and software-controllable. APPLICATIONS A simple 3-wire interface controls all on-chip registers. The Wireless infrastructure charge pump operates from a power supply ranging from 6 V to Microwave point-to-point/point-to-multipoint radios 30 V, whereas the rest of the device operates from 3.0 V to 3.6 V. VSAT radios The ADF4150HV can be powered down when not in use. Test equipment Private land mobile radios FUNCTIONAL BLOCK DIAGRAM SDV AV DV V R DD DD DD P SET MULTIPLEXER MUXOUT 10-BIT R 2 2 COUNTER DIVIDER REF IN DOUBLER LOCK LD DETECT CLK DATA DATA REGISTER HIGH VOLTAGE FUNCTION CHARGE CP LATCH OUT LE PUMP PHASE BOOST COMPARATOR MODE CURRENT SETTING RF + OUT OUTPUT DIVIDE-BY-1/ INTEGER FRACTION MODULUS STAGE -2/-4/-8/-16 RF VALUE VALUE VALUE OUT PDB RF THIRD-ORDER FRACTIONAL RF + RF IN INTERPOLATOR MULTIPLEXER INPUT RF IN N COUNTER ADF4150HV CE GND CP SD GND GND Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Trademarks and registered trademarks are the property of their respective owners. 09058-001ADF4150HV TABLE OF CONTENTS Features .............................................................................................. 1 Register 1 ..................................................................................... 17 Applications ....................................................................................... 1 Register 2 ..................................................................................... 17 General Description ......................................................................... 1 Register 3 ..................................................................................... 19 Functional Block Diagram .............................................................. 1 Register 4 ..................................................................................... 19 Revision History ............................................................................... 2 Register 5 ..................................................................................... 19 Specif icat ions ..................................................................................... 3 Register Initialization Sequence ............................................... 19 Timing Characteristics ................................................................ 5 RF SynthesizerA Worked Example ...................................... 20 Absolute Maximum Ratings ............................................................ 6 Reference Doubler and Reference Divider ............................. 20 Transistor Count ........................................................................... 6 12-Bit Programmable Modulus ................................................ 20 Thermal Resistance ...................................................................... 6 Spurious Optimization and Boost Mode ................................ 21 ESD Caution .................................................................................. 6 Spur Mechanisms ....................................................................... 21 Pin Configuration and Function Descriptions ............................. 7 Spur Consistency and Fractional Spur Optimization ........... 21 Typical Performance Characteristics ............................................. 9 Phase Resync ............................................................................... 22 Circuit Description ......................................................................... 11 Applications Information .............................................................. 23 Reference Input Section ............................................................. 11 Ultrawideband PLL .................................................................... 23 RF N Divider ............................................................................... 11 Microwave PLL ........................................................................... 23 Phase Frequency Detector (PFD) and High Voltage Generating the High Voltage Supply ....................................... 24 Charge Pump .............................................................................. 11 Interfacing to the ADuC702x and the ADSP-BF527 ............. 25 MUXOUT and Lock Detect ...................................................... 12 PCB Design Guidelines for a Chip Scale Package ................. 25 Input Shift Registers ................................................................... 12 Output Matching ........................................................................ 26 Program Modes .......................................................................... 12 Outline Dimensions ....................................................................... 27 Output Stage ................................................................................ 12 Ordering Guide .......................................................................... 27 Register Maps .................................................................................. 13 Register 0 ..................................................................................... 17 REVISION HISTORY 8/11Revision 0: Initial Version Rev. 0 Page 2 of 28