Fractional-N/Integer-N PLL Synthesizer Data Sheet ADF4151 FEATURES GENERAL DESCRIPTION Fractional-N synthesizer and integer-N synthesizer The ADF4151 allows implementation of fractional-N or RF bandwidth to 3.5 GHz integer-N phase-locked loop (PLL) frequency synthesizers 3.0 V to 3.6 V power supply if used with an external voltage controlled oscillator (VCO), 1.8 V logic compatibility loop filter, and external reference frequency. Separate charge pump supply (V ) allows extended tuning P The ADF4151 is used with external VCO parts and is footprint voltage (up to 5.5 V) in 3 V systems and software compatible with the ADF4350. The part consists Programmable dual-modulus prescaler of 4/5 or 8/9 of a low noise digital phase frequency detector (PFD), a precision Programmable RF output phase charge pump, and a programmable reference divider. There is 3-wire serial interface a - based fractional interpolator to allow programmable Analog and digital lock detect fractional-N division. The INT, FRAC, and MOD registers Switched bandwidth fast lock mode define an overall N divider N = (INT + (FRAC/MOD)) . The Cycle slip reduction RF output phase is programmable for applications that require APPLICATIONS a particular phase relationship between the output and the reference. The ADF4151 also features cycle slip reduction Wireless infrastructure (W-CDMA, TD-SCDMA, WiMax, GSM, circuitry, leading to faster lock times without the need for PCS, DCS, DECT) modifications to the loop filter. Test equipment Wireless LANs, CATV equipment Control of all the on-chip registers is through a simple 3-wire Clock generation interface. The device operates with a power supply ranging from 3.0 V to 3.6 V that can be powered down when not in use. The ADF4151 is available in a 5 mm 5 mm package. FUNCTIONAL BLOCK DIAGRAM SDV AV x DV V R DD DD DD P SET MULTIPLEXER MUXOUT 10-BIT R 2 2 COUNTER DIVIDER REF IN DOUBLER LOCK DETECT FL SWITCH SW O LD CLK DATA DATA REGISTER FUNCTION CHARGE CP LATCH OUT LE PUMP PHASE COMPARATOR INTEGER FRACTION MODULUS REG REG REG THIRD-ORDER FRACTIONAL INTERPOLATOR RF + IN N COUNTER RF IN ADF4151 CE A CP SD D GND GND GND GND Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 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All rights reserved. 10265-001ADF4151 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register 1 ..................................................................................... 17 Applications ....................................................................................... 1 Register 2 ..................................................................................... 17 General Description ......................................................................... 1 Register 3 ..................................................................................... 19 Functional Block Diagram .............................................................. 1 Register 4 ..................................................................................... 19 Revision History ............................................................................... 2 Register 5 ..................................................................................... 19 Specifications ..................................................................................... 3 Initialization Sequence .............................................................. 19 Timing Characteristics ................................................................ 5 RF SynthesizerA Worked Example ...................................... 20 Absolute Maximum Ratings ............................................................ 6 Modulus ....................................................................................... 20 Transistor Count ........................................................................... 6 Reference Doubler and Reference Divider ............................. 20 ESD Caution .................................................................................. 6 12-Bit Programmable Modulus ................................................ 20 Pin Configuration and Function Descriptions ............................. 7 Cycle Slip Reduction for Faster Lock Times ........................... 21 Typical Performance Characteristics ............................................. 9 Spurious Optimization and Fast lock ...................................... 21 Circuit Description ......................................................................... 11 Fast Lock Timer and Register Sequences ................................ 21 Reference Input Section ............................................................. 11 Fast LockAn Example ............................................................ 22 RF N Divider ............................................................................... 11 Fast LockLoop Filter Topology ............................................. 22 INT, FRAC, MOD, and R Counter Relationship.................... 11 Spur Mechanisms ....................................................................... 22 INT N Mode ................................................................................ 11 Spur Consistency and Fractional Spur Optimization ........... 23 R Counter .................................................................................... 11 Phase Resync ............................................................................... 23 Phase Frequency Detector (PFD) and Charge Pump ............ 11 Applications Information .............................................................. 24 MUXOUT and Lock Detect ...................................................... 12 Direct Conversion Modulator .................................................. 24 Input Shift Registers ................................................................... 12 Interfacing ................................................................................... 25 Program Modes .......................................................................... 12 PCB Design Guidelines for Chip Scale Package .................... 25 Register Maps .............................................................................. 13 Outline Dimensions ....................................................................... 26 Register 0 ..................................................................................... 17 Ordering Guide .......................................................................... 26 REVISION HISTORY 12/11Rev. A to Rev. B Changes to Normalized 1/f Noise Parameter, Table 1 ................. 4 11/11Rev. 0 to Rev. A Changes to Figure 28 ...................................................................... 23 10/11Revision 0: Initial Version Rev. B Page 2 of 28