High Voltage, Fractional-N/ Integer N PLL Synthesizer Data Sheet ADF4152HV FEATURES GENERAL DESCRIPTION Fractional-N synthesizer and integer N synthesizer The ADF4152HV is a 5.0 GHz, fractional-N or integer N High voltage charge pump: V = 6.0 V to 30 V frequency synthesizer with an integrated high voltage charge P Radio frequency (RF) bandwidth to 5.0 GHz pump. The synthesizer can drive external wideband voltage Programmable output divider controlled oscillators (VCOs) directly, eliminating the need for Synthesizer power supply: 3.0 V to 3.6 V operational amplifiers to achieve higher tuning voltages. The Programmable dual-modulus prescaler integrated high voltage charge pump simplifies design and Programmable output power level reduces cost while improving phase noise, in contrast to active Programmable charge pump currents filter topologies, which tend to degrade phase noise compared RF output mute function to passive filter topologies. 3-wire serial interface The VCO frequency can be divided by 1, 2, 4, 8, or 16 to allow Analog and digital lock detect the user to generate RF output frequencies as low as 31.25 MHz. APPLICATIONS For applications that require isolation, the RF output stage can be muted. The mute function is both pin and software controllable. Wireless infrastructure Microwave point to point/point to multipoint radios A simple 3-wire interface controls all on-chip registers. The Very small aperture terminal (VSAT) radios charge pump operates from a power supply ranging from 6.0 V Test equipment to 30 V, whereas the rest of the device operates from 3.0 V to Private land mobile radios 3.6 V. The ADF4152HV can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM SDV AV DV V R DD DD DD P SET MULTIPLEXER MUXOUT 10-BIT R 2 2 COUNTER DIVIDER REF DOUBLER IN LOCK LD DETECT CLK DATA DATA REGISTER HIGH VOLTAGE FUNCTION CHARGE CP LATCH OUT LE PUMP PHASE BOOST COMPARATOR MODE CURRENT SETTING RF + OUT OUTPUT 1/2/ INTEGER FRACTION MODULUS STAGE 4/8/16 RF VALUE VALUE VALUE OUT PDB RF THIRD-ORDER FRACTIONAL RF RF + IN INTERPOLATOR MULTIPLEXER INPUT RF IN N COUNTER ADF4152HV CE GND CP SD GND GND Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 14382-001ADF4152HV Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register 0 ..................................................................................... 14 Applications ....................................................................................... 1 Register 1 ..................................................................................... 15 General Description ......................................................................... 1 Register 2 ..................................................................................... 16 Functional Block Diagram .............................................................. 1 Register 3 ..................................................................................... 18 Revision History ............................................................................... 2 Register 4 ..................................................................................... 19 Specifications ..................................................................................... 3 Register 5 ..................................................................................... 20 Timing Characteristics ................................................................ 5 Register Initialization Sequence ............................................... 20 Absolute Maximum Ratings ............................................................ 6 RF SynthesizerA Worked Example ...................................... 20 Transistor Count ........................................................................... 6 Reference Doubler and Reference Divider ............................. 21 Thermal Resistance ...................................................................... 6 12-Bit Programmable Modulus ................................................ 21 ESD Caution .................................................................................. 6 Spurious Optimization and Boost Mode ................................ 21 Pin Configuration and Function Descriptions ............................. 7 Spur Mechanisms ....................................................................... 21 Typical Performance Characteristics ............................................. 9 Spur Consistency and Fractional Spur Optimization ........... 22 Theory of Operation ...................................................................... 11 Phase Resync ............................................................................... 22 Reference Input Section ............................................................. 11 Applications Information .............................................................. 23 RF N Divider ............................................................................... 11 Ultrawideband PLL .................................................................... 23 Phase Frequency Detector (PFD) and High Voltage Charge Microwave PLL ........................................................................... 23 Pump ............................................................................................ 11 Generating the High Voltage Supply ....................................... 24 MUXOUT and Lock Detect ...................................................... 12 Interfacing to the ADuC702x and the ADSP-BF527 ............ 25 Input Shift Registers ................................................................... 12 PCB Design Guidelines for a Chip Scale Package ................. 25 Program Modes .......................................................................... 12 Output Matching ........................................................................ 26 Output Stage ................................................................................ 12 Outline Dimensions ....................................................................... 27 Register Maps .................................................................................. 13 Ordering Guide .......................................................................... 27 REVISION HISTORY 7/2016Revision 0: Initial Version Rev. 0 Page 2 of 27