Fractional-N Frequency Synthesizer Data Sheet ADF4153A FEATURES GENERAL DESCRIPTION RF bandwidth to 4 GHz The ADF4153A is a fractional-N frequency synthesizer 2.7 V to 3.3 V power supply that implements local oscillators in the upconversion and Separate V allows extended tuning voltage P downconversion sections of wireless receivers and transmit- Programmable fractional modulus ters. It consists of a low noise digital phase frequency detector Programmable charge pump current (PFD), a precision charge pump, and a programmable reference 3-wire serial interface divider. A sigma-delta (-) based fractional interpolator Analog and digital lock detect allows programmable fractional-N division. The INT, FRAC, Power-down mode and MOD registers define an overall N divider (N = (INT + Pin-compatible with ADF4106, ADF4110/ADF4111/ (FRAC/MOD))). In addition, the 4-bit reference counter (R ADF4112/ADF4113, and ADF4153 counter) allows selectable REFIN frequencies at the PFD input. Consistent RF output phase A complete phase-locked loop (PLL) can be implemented if the Loop filter design possible with ADIsimPLL synthesizer is used with an external loop filter and a voltage controlled oscillator (VCO). APPLICATIONS A simple 3-wire interface controls all on-chip registers. CATV equipment The device operates with a power supply ranging from Base stations for mobile radio (GSM, PCS, DCS, WiMAX, 2.7 V to 3.3 V and can be powered down when not in use. SuperCell 3G, CDMA, W-CDMA) Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA) Wireless LANs, PMR Communications test equipment FUNCTIONAL BLOCK DIAGRAM AV DV V SDV R DD DD P DD SET ADF4153A REFERENCE 4-BIT 2 R COUNTER REF IN DOUBLER + PHASE CHARGE CP FREQUENCY PUMP DETECTOR V DD HIGH-Z DGND LOCK CURRENT DETECT SETTING OUTPUT MUXOUT V DD MUX R DIV RFCP3 RFCP2 RFCP1 N DIV RF A IN N-COUNTER RF B IN THIRD ORDER FRACTIONAL INTERPOLATOR CLK FRACTION MODULUS INTEGER 24-BIT DATA REG REG REG DATA REGISTER LE AGND DGND CPGND Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20122013 Analog Devices, Inc. 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Technical Support www.analog.com 11047-001ADF4153A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 N Divider Register, R0 ............................................................... 15 Applications ....................................................................................... 1 R Divider Register, R1................................................................ 15 General Description ......................................................................... 1 Control Register, R2 ................................................................... 15 Functional Block Diagram .............................................................. 1 Noise and Spur Register, R3 ...................................................... 16 Revision History ............................................................................... 2 Reserved Bits ............................................................................... 16 Specifications ..................................................................................... 3 Initialization Sequence .............................................................. 17 Timing Specifications .................................................................. 4 RF Synthesizer: A Worked Example ........................................ 17 Absolute Maximum Ratings ............................................................ 5 Modulus ....................................................................................... 17 ESD Caution .................................................................................. 5 Reference Doubler and Reference Divider ............................. 17 Pin Configurations and Function Descriptions ........................... 6 12-Bit Programmable Modulus ................................................ 17 Typical Performance Characteristics ............................................. 7 Fastlock with Spurious Optimization ...................................... 18 Circuit Description ........................................................................... 8 Spur Mechanisms ....................................................................... 18 Reference Input Section ............................................................... 8 Spur Consistency ........................................................................ 19 RF Input Stage ............................................................................... 8 Phase Resync ............................................................................... 19 RF INT Divider ............................................................................. 8 Filter DesignADIsimPLL....................................................... 19 INT, FRAC, MOD, and R Relationship ..................................... 8 Interfacing ................................................................................... 19 RF R Counter ................................................................................ 8 PCB Design Guidelines for Chip Scale Package .................... 20 Phase Frequency Detector (PFD) and Charge Pump .............. 9 Applications Information .............................................................. 21 MUXOUT and Lock Detect ........................................................ 9 Local Oscillator for a GSM Base Station Transmitter ........... 21 Input Shift Registers ..................................................................... 9 Outline Dimensions ....................................................................... 22 Program Modes ............................................................................ 9 Ordering Guide .......................................................................... 22 Register Maps .................................................................................. 10 REVISION HISTORY 1/13Rev. 0 to Rev. A Added TSSOP Package ...................................................... Universal Added Figure 3, Renumbered Sequentially ................................... 6 Updated Outline Dimensions ........................................................ 22 Changes to Ordering Guide ........................................................... 22 10/12Revision 0: Initial Version Rev. A Page 2 of 24